The AT91SO100/101, AT91SO50/51 and the AT91SO25 are a low-power, high-performance, SC100 32-bit microcontroller based on the ARM® enhanced RISC architecture.
This new SC100 core allows the linear addressing of up to 1M bytes of code and data as well as a number of new functional and security features.
A 3-level instruction pipeline allows the performance of one instruction in a single clock cycle, the SC100 achieves throughputs close to 1 MIPS per MHz.
The SC100 processor employs a unique architectural strategy known as Thumb® a super reduced instruction set that is ideally suited for high volume applications with memory restrictions and applications where code density is an important factor.