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  • Disruptive Logic Architectures and Technologies
    T. Ernst, E. Bernard, C. Dupre, A. Hubert, S. Becu, B. Guillaumot, O. Rozeau, O. Thomas, P . Coronel, J.-M. Hartmann, C … … Skotnicki, S. Deleonibus, 3D multi channels and stacked nanowires technologies … … Design and Technology and Tutorial ,ICICDT 2008. pp. 265–268 … … P. Robert, O. Faynot, Novel Si-based nanowire devices: will they serve ultimate MOSFETs scaling or ultimate …
  • A two-dimensional analytical-model-based comparative threshold performance analysis of SOI-SON MOSFETs
    IEEE International Conference on Integrated Circuit Design and Technology and Tu- torial , 2008: 1 [16] Young K K. Short- channel effect in fully depleted SOI MOS- FET ’s. IEEE Trans Electron Devices, 1989, 36(2): 399 [17] Yeh P C, Fossum J G. Physical subthreshold …
  • SDW MOSFETs in LSI analog circuit design
    M. H. Elsaid and M. I. Elmasry, “Scaling merged SDW MOSFET ’S for VLSI,” Solid-State … Y. P . Tsividis, “Design considerations in single- channel MOS ana- log integrated circuits-A tutorial ;’ IEEE J, Solid-state Circuits, vol.
  • Charge-pumping extraction techniques for hot-carrier induced interface and oxide trap spatial distributions in MOSFETs
    International Reliability Physics Symposium (IRPS), tutorial , 2010. [10] I. Starkov, S. Tyaginov, H. Enichlmair, J. Park, T. Grasser, and C. Junge- mann, “Analysis of worst-case hot-carrier degradation conditions in the case of n- and p - channel high-voltage MOSFETs ,” in International Con- ference on Simulation of …
  • Nonuniform Mobility-Enhancement Techniques and Their Impact on Device Performance
    [10] S. Takagi, M. Iwase, and A. Toriumi, “On the universality of inversion layer mobility in n and p channel MOSFETs ,” in IEDM Tech. Dig., Dec. 1988, pp. 398–401. IEDM Short Course, IEDM’99 Tutorial , 1999.
  • Self-cascode SOI versus graded-channel SOI MOS transistors
    … 7 Pavanello, M.A., Martino, J.A., and Flandre, D.: ‘Analog circuit design using graded-channel silicon-on-insulator nMOSFETs’, Solid- State Electron., 2002, 46, pp. 1215–1225 8 Gimenez, S. P ., Pavanello, M.A., Martino … … gain by using graded- channel SOI nMOSFETs’. … Yan, S., and Sanchez-Sinencio, E.: ‘Low voltage analog circuit design techniques: a tutorial ’, IEICE Fundam. … B., Rao, V.R., and Woo, J.C.S.: ‘Sub-0.18mm SOI MOSFET using lateral asymmetric …
  • Development of a CMOS cell library for RF wireless and telecommunications applications
    … assistance to the RF design community, the CIF layout files, test data and tutorials are available from … All the cells being investigated were fabricated using 2.0, 1.2 and 0.8 micron (µm) silicon CMOS n-well processes using both n- channel and p -channel enhancement MOSFETs using MOSIS.
  • Device design methodology and reliability strategy for deep sub-micron technology [DRAMs]
    TUTORIALS The effect of increasing the MOSFET well doping to compensate for short channel behavior is illustrated in figure 3. The measuredemission probability ( P =I&) is shown to increase by two orders of magnitude for the HD …
  • Hot carrier degradation and ESD in submicrometer CMOS technologies: how do they interact?
    IRPS Tutorial . … G. Van den Bosch, and H. E. Maes, “Hot carrier degradation in submicrometre MOSFET ’s: From uniform … [8] P . Heremans, R. Bellens, G. Groeseneken, and H. E. Maes, “Consis- tent model for the hot carrier degradation in n- channel and p-channel MOSFET’s,” IEEE Trans.
  • The Universality of NBTI Relaxation and its Implications for Modeling and Characterization
    [34] C. Schlunder, W. Heinrigs, W. Gustin, and H. Reisinger, "On the Impact of NBTI Recovery Phenomena on Lifetime Prediction of modern p - MOSFETs ," in IIRW Final Rep., 2006, pp. 1-4. … M.A. Alam, "NBTI A Simple View of a Complex Phenomena," in Proc. IRPS, 2006, ( Tutorial ). … Parthasarathy, N. Revil, and E. Vincent, "Modeling Negative Bias Temperature Instabilities in Hole Channel Metal-Oxide-Semiconductor …
  • Reduction of power MOSFET losses in hard-switched converters
    1 Dodge, J.: ‘Power MOSFET tutorial ’, Advanced Power Technology applications guide, (Microsemi application note) 2 Ferreira, A., and Simas, M.I.C.: ‘Power MOSFETs reverse conduction revisited’. Power Electronics Specialists Conf., June 1991, pp. 416–422 3 Jinno, M., Chen, P .-Y., and Shie, Y … … 4 Huselstein, J.-J., Gauthier, C., and Glaize, C.: ‘Use of the MOSFET channel reverse conduction in …
  • Enhancement of electron mobility in ultrathin-body silicon-on-insulator MOSFETs with uniaxial strain
    … Klaus, B. McIntyre, K. Mistry, A. Murthy, T. Sandford, M. Silberstein, S. Sivakumar, P . Smith, K. Za … [6] K. Uchida, J. Koga, R. Ohba, T. Numata, and S. I. Takagi, “Experi- mental evidence of quantum-mechanical effects on low-field mobility, gate- channel capacitance, and threshold voltage of ultrathin body SOI MOSFETs ,” in IEDM Tech. Dig., 2001, pp … [7] S. Hasan, Schred 2.1 Tutorial .
  • Compact Modeling of MOSFET Wearout Mechanisms for Circuit-Reliability Simulation
    Tutorial Notes. … H. Chou et al., “Negative bias temperature instability (NBTI) in deep sub-micron p +-gate pMOSFETs,” … Do, T. Q. Vu, G. Warren et al., “Negative bias instability in silicon- on-sapphire n- channel MOSFETs ,” in Proc. IEEE Int. SOI Conf., 1998, pp. 85–86.
  • A non-quasi-static MOSFET model for SPICE-AC analysis
    H. J. Park, “Charge sheet and non-quasistatic MOSFET models for SPICE,” Ph.D. dissertation, Electron … B. J. Sheu, D. L. Scharfetter, P . K.KO, and M. C. Jeng, “BSIM: Berkeley short channel IGFET model for MOS transistors,” IEEE J. Solid-state Circuits, vol. P. R. Gray and R. G. Meyer, “MOS operational amplifier design- A tutorial overview,” IEEE J …
  • Analysis and modelling of initial delay time and its impact on propagation delay of CMOS logic gates
    University of California, Berkeley, CA, USA, 1975 9 RICHMAN, P .: ‘MOS field-effect transistor and integrated circuits’ (John Wiley Inc., New York, 1973) 10 YAU, L.D.: ‘A simple theory to predict the threshold voltage of short- channel IGFETs’, Solid-State Electron … I I ELMASRY, M.I ‘Digital MOS integrated circuits: A Tutorial ’, in ‘Digital MOS Integrated Circuits’ … … RIDEOUT, V.L., BASSOUS, E., and LABLANE, A.R.: ’Design of ion-implanted MOSFETs with very small …