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Macrocells:

System Gates:

Product Terms per Macrocell:

Registers:

Logic Cells / Logic Blocks:

Look-Up-Tables (LUTs):

IC Package Type:

Pin Count:

Operating Temperature:

Allow up to: overrange/margin
Use the overrange/margin to restrict your search to items whose full-scale range is close to your requirements.
(Overrange/margin requires both 'From' and 'To' values to work.)

Internal Frequency:

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pins

Speed Grade:

Propagation Delay:

Supply Voltage:

Operating Current:

Standby Current:

Power Dissipation:

Help with Programmable Logic Devices (PLD) specifications:

General Specifications
   Device Type       
   Your choices are...         
   SPLD       Simple programmable logic devices (SPLD) are the simplest, smallest and least-expensive forms of programmable logic devices. SPLDs can be used in boards to replace 7400-series TTL components (AND, OR, and NOT gates). They typically comprise 4 to 22 fully connected macrocells. These macrocells are typically comprised of some combinatorial logic (such as AND and OR gates) and a flip-flop. In other words, a small Boolean logic equation can be built within each macrocell. This equation will combine the state of some number of binary inputs into a binary output and, if necessary, store that output in the flip-flop until the next clock edge. Of course, the particulars of the available logic gates and flip-flops are specific to each manufacturer and product family. But the general idea is always the same. Most SPLDs use either fuses or non-volatile memory cells (EPROM, EEPROM, FLASH, and others) to define the functionality. These devices are also known as programmable array logic (PAL), generic array logic (GAL), programmable logic arrays (PLA), or field-programmable logic arrays (FPLA), and programmable logic devices (PLD). PLDs are often used for address decoding, where they have several clear advantages over the 7400-series TTL parts that they replaced. First, one chip requires less board area, power, and wiring than several do. Another advantage is that the design inside the chip is flexible, so a change in the logic does not require any rewiring of the board. Rather, simply replacing one PLD with another part that has been programmed with the new design can alter the decoding logic. 
   CPLD       Complex programmable logic devices (CPLD) are similar to SPLDs, but they have a significant higher capacity.  CPLDs typically contain from ten to several hundred macrocells.  Several logic blocks form a typical CPLD.  A logic block is a group of eight to 16 macrocells that together perform a specific function. The macrocells within a function block are fully connected, but all the function blocks are not necessarily connected. CPLDs are also known as erasable programmable logic devices (EPLD), programmable electrically erasable logic (PEEL) devices, electrically erasable programmable logic devices (EEPLD), multiple array matrix (MAX), and others. CPLDs do not have as much logic as FPGAs; only up to 10,000 gates. But CPLDs offer very predictable timing characteristics and are therefore ideal for critical control applications. Some CPLDs require extremely low amounts of power and are very inexpensive, making them ideal for cost-sensitive, battery-operated, portable applications such as mobile phones and digital handheld assistants. Because CPLDs can hold larger designs than PLDs, their potential uses are more varied. They are still sometimes used for simple applications like address decoding, but more often contain high-performance control-logic or complex finite state machines. At the high-end (in terms of numbers of gates), there is also a lot of overlap in potential applications with FPGAs. Traditionally, CPLDs have been chosen over FPGAs whenever high-performance logic is required. Because of its less flexible internal architecture, the delay through a CPLD (measured in nanoseconds) is more predictable and usually shorter. 
   FPGA       Field programmable gate arrays (FPGAs) have a different architecture than SPLDs and CPLDs, and typically offer higher capacity.  FPGAs consist of an array of logic blocks, surrounded by programmable I/O blocks that are connected by programmable interconnects. FPGAs contains from 64 to tens of thousands of logic blocks and an even greater number of flip-flops. Like the CPLDs, FPGAs do not provide 100% interconnect between logic blocks (this would be prohibitively expensive). FPGAs are also known as logic cell arrays (LCA) and programmable ASIC (pASIC). FPGAs are used in a wide variety of applications ranging from data processing and storage, to instrumentation, telecommunications, and digital signal processing. 
   FPIC       Field-programmable interconnect chips (FPIC), also known as field-programmable interconnect devices (FPID), are not really a logic devices, but rather programmable "wiring" devices. Through programming, FPICs connect one pin to another providing programmable interconnects. FPICs use either SRAM or anti-fuse programming technology. 
   SERDES       Serializer / deserializer (SERDES) are macrocell circuits that receive fast serial signals (in the order of Mbits/s, or higher) and deserialize them to slower parallel signals. Some SERDES can be programmed like any other PLD. 
   IC Core       IC cores (also known as embedded cores) are bare die semiconductor chips used as system building blocks. IC cores can contain memory, microprocessor, I/O interfaces, FPGAs and other components. Embedded cores generally lower system costs and shorten the time-to-market. 
   Other       Other unlisted, specialized, or proprietary logic devices. 
   Search Logic:      All products with ANY of the selected attributes will be returned as matches. Leaving all boxes unchecked will not limit the search criteria for this question; products with all attribute options will be returned as matches.
   Macrocells:       Macrocells on most modern SPLDs or CPLDs contain sum-of-product combinatorial logic function and an optional flip-flop. The combinatorial logic function typically supports four to sixteen product terms with wide fan-in. 
   Search Logic:      User may specify either, both, or neither of the "At Least" and "No More Than" values. Products returned as matches will meet all specified criteria.
   System Gates:       The total number of logic gates in the device. 
   Search Logic:      User may specify either, both, or neither of the "At Least" and "No More Than" values. Products returned as matches will meet all specified criteria.
   Product Terms per Macrocell:       The number of product terms that can be managed by a macrocell.  Product terms are the product of digital signals that perform a particular logic function. 
   Search Logic:      User may specify either, both, or neither of the "At Least" and "No More Than" values. Products returned as matches will meet all specified criteria.
   Registers:       The total number of shift registers in the device. 
   Search Logic:      User may specify either, both, or neither of the "At Least" and "No More Than" values. Products returned as matches will meet all specified criteria.
   Logic Cells / Logic Blocks       The number of logic cells in the device. Logic cells (LC) are blocks or modules inside the chip, not including the I/O blocks. They generally contain a look-up table to generate any function of inputs, a clocked latch (flip-flop) to provide registered outputs, and control logic circuits for configuration purposes. They are also knows as logic array blocks (LAB), logic elements (LE) and configurable logic blocks (CLB). 
   Search Logic:      User may specify either, both, or neither of the "At Least" and "No More Than" values. Products returned as matches will meet all specified criteria.
   Look-Up-Tables (LUTs)       The number of look-up tables (LUT) available in the device. Look-up tables are truth tables used to implement a single logic function by storing the correct output logic state in a memory location that corresponds to each particular combination of input variables. 
   Search Logic:      User may specify either, both, or neither of the "At Least" and "No More Than" values. Products returned as matches will meet all specified criteria.
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Package Characteristics
   IC Package Type       
   Your choices are...         
   PBGA       Plastic ball-grid array (PBGA) is the general terminology for the BGA package adopting plastic (epoxy molding compound) as the encapsulation. According to JEDEC standard, PBGA refers to an overall thickness of over 1.7mm. 
   TBGA       Tape ball-grid array (TBGA) uses a fine, polyimide substrate and provides good thermal performance with high pin counts. 
   SBGA       Super ball-grid array (SBGA) provides a high-power BGA package with a very low profile. With SGBA, the IC is directly attached to an integrated copper heatsink. Since the IC and I/O are on the same side, signal vias are eliminated, providing a significant improvement in electrical performance (inductance). 
   FLGA       Fine-pitch land-grid array (FLGA) is extremely compact and lightweight, making it suitable for miniature disc drives and digital cameras. 
   QFP       Quad flat packages (QFP) contain a large number of fine, flexible, gull wing shaped leads. Lead width can be as small as 0.16 mm. Lead pitch is 0.4 mm. QFPs provide good second-level reliability and are used in processors, controllers, ASICs, DSPs, gate arrays, logic, memory ICs, PC chipsets, and other applications.  
   LQFP       Low quad flat package (LQFP). 
   TQFP       Thin quad flat package (TQFP). 
   PQFP       Plastic quad flat package (PQFP). 
   SOP       Small outline package (SOP) 
   SOIC       Small outline integrated circuit (SOIC). 
   TSOP, Type I and II       Thin small outline package (TSOP) is a type of DRAM package that uses gull wing shaped leads on both sides. TSOP DRAM mounts directly on the surface of the printed circuit board. The advantage of the TSOP package is that it is one-third the thickness of an SOJ package. TSOP components are commonly used in small outline DIMM and credit card memory applications. Thin small outline package may be Type I or Type II. 
   SSOP       Shrink small outline package (SSOP). 
   TSSOP       Thin shrink small outline L-leaded package (TSSOP). 
   TVSOP       Thin very small outline package (TVSOP). 
   SOJ       Small outline J-lead (SOJ) is a common form of surface-mount DRAM packaging. It is a rectangular package with J-shaped leads on the two long sides of the device. 
   HSOF       Small outline flat-leaded package with heat sink (HSOF). 
   PLCC       Plastic leaded chip carrier (PLCC). 
   LCCC       Leadless ceramic chip carrier (LCCC). 
   PDIP       Plastic dual in-line package (PDIP) is widely used for low cost, hand-insertion applications including consumer products, automotive devices, logic, memory ICs, micro-controllers, logic and power ICs, video controllers commercial electronics and telecommunications. 
   CDIP       Ceramic dual in-line package (CDIP) consists of two pieces of dry pressed ceramic surrounding a "DIP formed" lead frame. The ceramic / LF / ceramic system is held together hermetically by frit glass reflowed at temperatures between 400° - 460° centigrade. 
   SIP       Single in-line package (SIP). 
   SDIP       Shrink dual in-line package (SDIP). 
   SZIP       Shrink zigzag in-line package (SZIP). 
   Other       Other unlisted, specialized, or proprietary IC packages. 
   Search Logic:      Products with the selected attribute will be returned as matches. Leaving or selecting "No Preference" will not limit the search criteria for this question; products with all attribute options will be returned as matches.
   Pin Count       Total number of pins in the package. 
   Search Logic:      User may specify either, both, or neither of the "At Least" and "No More Than" values. Products returned as matches will meet all specified criteria.
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Performance
   Operating Temperature:       This is the full-required range of ambient operating temperature. 
   Search Logic:      User may specify either, both, or neither of the limits in a "From - To" range; when both are specified, matching products will cover entire range. Products returned as matches will meet all specified criteria.
   Internal Frequency:       Internal frequency is the speed (in MHz) at which the device can perform operations or data transfers internally. Once the data is in the device, some type of processing (read, write, move, etc.) takes place. 
   Search Logic:      All matching products will have a value greater than or equal to the specified value.
   User I/Os:       The total number of user I/O ports available. 
   Search Logic:      All matching products will have a value greater than or equal to the specified value.
   Speed Grade:       The speed grade indicates the delay in nanoseconds (ns) through a macrocell in the device. For example, a device with a -10 speed grade has a delay of 10ns through a macrocell. Devices with low speed grade numbers run faster than devices with high-speed grade numbers. 
   Search Logic:      All matching products will have a value less than or equal to the specified value.
   Propagation Delay:       This is the time interval between the application of an input signal and the occurrence of the corresponding output in a logic circuit. 
   Search Logic:      All matching products will have a value less than or equal to the specified value.
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Power Characteristics
   Supply Voltage:       
   Your choices are...         
   -5 V       The chip operates with -5 volts. 
   -4.5 V       The chip operates with -4.5 volts. 
   -3.3 V       The chip operates with -3.3 volts. 
   -3 V       The chip operates with -3 volts. 
   1.2 V       The chip operates with 1.2 volts. 
   1.5 V       The chip operates with 1.5 volts. 
   1.8 V       The chip operates with 1.8 volts. 
   2.5 V       The chip operates with 2.5 volts. 
   3 V       The chip operates with 3 volts. 
   3.3 V       The chip operates with 3.3 volts. 
   3.6 V       The chip operates with 3.6 volts. 
   5 V       The chip operates with 5 volts. 
   Other       Other unlisted supply voltages. 
   Search Logic:      All products with ANY of the selected attributes will be returned as matches. Leaving all boxes unchecked will not limit the search criteria for this question; products with all attribute options will be returned as matches.
   Operating Current       The minimum current needed for active chip operation. 
   Search Logic:      All matching products will have a value less than or equal to the specified value.
   Standby Current       The minimum current needed to maintain the chip while it is inactive. 
   Search Logic:      All matching products will have a value less than or equal to the specified value.
   Power Dissipation       The total power consumed by the device. 
   Search Logic:      All matching products will have a value less than or equal to the specified value.
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