J-K Flip-Flops Datasheets

Logic - Flip Flops -- 1727-2003-ND
from Digi-Key Electronics

IC JK TYPE NEG TRG DUAL 14SOIC [See More]

  • Flip-Flop Type: J-K
  • Supply Voltage: 2.5V; 3V; 3.3V; 3.6V; 5V; 2 V ~ 6 V
  • Triggering: Negative-edge Triggered
  • Output Characteristics: Differential
Flip-Flops DUAL J-K W/NEG-EDGE -- 74HC107D [74HC107D from NXP]
from Karl Kruse GmbH & Co. KG

Karl Kruse  is a worldwide leading franchised distributor (ISO: 9001-2008 certified). A service provider specializing in the supply and material management of electronic components, since 1951. We are an innovative company who is dedicated to collaborating with customers and partners to develop... [See More]

  • Flip-Flop Type: J-K
  • Triggering: Negative-edge Triggered
Clock and Data Distribution - Registers and Flip Flops Products -- SY100EL35
from Microchip Technology, Inc.

The SY10/100EL35 are high-speed JK Flip-Flops. The J/K data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave and, thus, the outputs, upon a positive transition of the clock. The reset pin is asynchronous and is activated with a logic HIGH. [See More]

  • Flip-Flop Type: J-K
  • fMAX: 2200
  • Supply Voltage: 5V
  • Package Type: SOIC-8; SOIC
1219229 [CD74HC73E from Texas Instruments Standard Linear and Logic]
from RS Components, Ltd.

Texas Instruments range of Flip-Flops and Latches from the 74HC Family of CMOS Logic ICs. The 74HC Family use silicon gate CMOS technology to achieve operating speeds similar to the LSTTL family but with the low power consumption of standard CMOS integrated circuits. Logic Family = HC. Logic... [See More]

  • Flip-Flop Type: J-K
  • Package Type: PDIP
  • Triggering: Negative-edge Triggered
  • Logic Family: HCMOS
CD54AC109 Dual Positive-Edge Triggered J-K Flip-Flops with Set and Reset -- CD54AC109F3A
from Texas Instruments

Dual Positive-Edge Triggered J-K Flip-Flops with Set and Reset 16-CDIP -55 to 125 [See More]

  • Flip-Flop Type: J-K
  • Package Type: CDIP
  • Triggering: Positive-edge Triggered
  • Logic Family: AC
Flip-Flop, Master-Slave; Dual J-K Master-Slave; 20 V; 500 mW; 5 pF (Typ.) -- 70147196
from Allied Electronics, Inc.

PDIP Package Type, CMOS Dual J-K Master-Slave Flip-Flop. Set-Reset capability. Medium speed operation. Maximum input current. The CD4027B types are sapplied in 16-lead hermetic Dual In Line ceramic packages (F3A suffix), 16-lead Dual In Line plastic packages (E suffix), 16-lead small-outline... [See More]

  • Flip-Flop Type: J-K
  • Power Dissipation: 500
  • Triggering: Master-slave
  • Operating Temperature: -55 to ?
AND Input J-K Flip-Flop -- 3155/C,A
from Lansdale Semiconductor, Inc.

TTL III integrated circuits comprise a family of transistor-transistor logic designed for general purpose digital applications. The family has a high operating speed (30-50 MHz clock rate), good external noise immunity, high fan-out, and the capability of driving lines up to 600pF capacitance. [See More]

  • Flip-Flop Type: J-K
  • Propagation Delay: 10
  • Supply Voltage: 4.5-5.5 VDC
  • Power Dissipation: 80
FF/Latch -- M38510/00201BCA
from Rochester Electronics

TTL/H/L SERIES, NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP14 [See More]

  • Flip-Flop Type: J-K
  • Supply Voltage: 5V
  • Triggering: Negative-edge Triggered
  • Output Characteristics: Complementary Output
FF/Latch -- M38510/00203BCX
from Sarnoff Corporation

TTL/H/L SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP14 [See More]

  • Flip-Flop Type: J-K
  • Supply Voltage: 5V
  • Triggering: Negative-edge Triggered
  • Output Characteristics: Complementary Output