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Quality, Test & Measurement
September 15, 2010 View Agenda

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4:00 PM - 5:00 PM EDT (1:00 PM - 2:00 PM PDT)
Accessing the Value-add of DFT and Test

While test and design-for-testability provide real bottom line value, there is a wide degree of variance in the success with which test and DFT are applied across the industry, particularly in terms of cost-effectiveness. Attendees to this presentation will learn how to use industry benchmark data to improve the value derived from testing and DFT. Participants of the discussion will also explore two subjects that directly impact test strategy: dealing with defects in power-management circuitry, and exposing test features to customers for use at higher levels of integration. Far from being just a pitch for more DFT, this presentation gives guidance on how to select the appropriate level of DFT for the situation and argues that it is quite possible to over-invest in DFT and test application.

Key Take-Aways:
  • Understand why test and DFT add value to your products and processes
  • Discover basic approaches to assessing the value-add of test and DFT
  • Learn the latest developments in re-using test features across the entire life-cycle of a product
Jeff Rearick, AMD Fellow, AMD

As leader of AMD's DFT Center of Expertise, Jeff Rearick directs company efforts to enhance the design-for-testability features of AMD's leading edge microprocessors. Rearick also serves as the editor of the IEEE P1687 standard and is a member of the program committee for the International Test Conference. Prior to joining AMD, he spent 22 years at HP and Agilent. Rearick holds a BSEE degree from Purdue University and an MSEE degree from the University of Illinois. He has been granted 20 U.S. patents and has received numerous awards for his technical publications in the field of testing integrated circuits.

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