Multiband architecture for high-speed SerDes
In this paper, we explore a multiband architecture for a 25 Gbps SerDes , where the channel in each sub-band is approximately frequency flat, eliminating need of an equalizer in the receiver.
Scientist Highlights Steps To Developing 100 Gigabit Ethernet Standard
A fundamentally new way of designing backplanes and having a 25 Gbps SERDES [serializer/deserializer] developed within the OIF will be the 100 Gig enablers the industry requires to move the technology forward." .
The Migration of the Optical Internetworking Forum Common Electrical Interface Standardization to Optical Intra‐System Interconnects Beyond 25 Gb/s
 C. Y. Liu and J. Caroselli, “Comparison of
Signaling and Equalization Schemes in High
Speed SerDes (10- 25Gbps ),” Proc. IEC
DesignCon (Santa Clara, CA, 2007).
Beyond 10 Gbps? Challenges of Characterizing Future I/O Interfaces with Automated Test Equipment
 Cathy Liu and Joe Caroselli, "Comparison of
Signaling and Equalization Schemes in High Speed SerDes (10- 25Gbps )," Proceedings of the IEC
Semtech Completes Acquisition of Gennum Corporation
Combining Gennum's 1 Gbps to 25 Gbps signal integrity solutions with Semtech's 40 Gbps to 100 Gbps SerDes solutions creates one of the industry's most complete and robust analog and mixed signal portfolios targeted at the communications and enterprise computing segments," …
Semtech Announces Plans to Acquire Gennum Corporation
We believe Gennum’s unique signal integrity solutions and highly differentiated 1 Gbps to 25 Gbps optical products combined with Semtech’s leading 40 Gbps and 100 Gbps SerDes portfolio will deliver one of the industry’s most complete and robust portfolios to the communications …
Broadcom Backplane Fits in Foundry | Light Reading
The integration of multiple 3.125 Gigabits per second ( Gbps ) serializer/deserializer ( SerDes ) channels with 7 million bits of custom SRAM (static random access memory … … chip eliminates over 1,500 pins and reduces power by more than 25 % versus comparable discrete …
A 28Gbps 4×4 switch with low jitter SerDes using area-saving RF model in 0.13μm CMOS technology
throughput of this 4 4 load-balanced switch circuit with quad SerDes interface is about 28 Gbps . … Birkhoff-von
Neumann switches, part I: one-stage buffering,” Computer
Communications, Vol. 25 , pp. 611-622 …
Enabling terabit per second switch linecard design through chip/package/PCB co-design
The main goal of the
simulation is to validate the possibility of enabling 25 Gbps data rate for the entire chip/package/PCB channel designed. The simulation results are also used to study the potential
implementation requirements of future SerDes technologies.
A low-cost wire-bonding package design with package built-in three-dimensional distributed matching circuit for over 5Gbps SerDes applications
The three-dimensional distributed matching circuit has
been applied to the two-metal layer wire-bonding package for
6.4 Gbps SerDes device. … to that of the standard 50 Ohm design (100 Ohm
in differential mode, 25 Ohm in common …