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Products/Services for 40 Gbps SerDes For Transceiver

  • Serdes-Image
    Serdes - (14 companies)
    Serializer/de-serializer (SERDES) macro-cell circuits receive fast serial signals (on the order of Mbits/s or higher) and de-serialize them into slower parallel signals. Some SERDES circuits can be programmed like any other PLD. SERDES Information... Search by Specification | Learn More
  • RF Transceivers-Image
    RF Transceivers - (271 companies)
    RF transceivers are electronic devices that receive and demodulate an RF signal, then modulate and transmit a new signal. RF Transceivers Information. RF transceivers are electronic devices that receive and demodulate radio frequency (RF) signals... Search by Specification | Learn More
  • Fiber Optic Transceivers-Image
    Fiber Optic Transceivers - (225 companies)
    Specifications. The GlobalSpec SpecSearch database characterizes fiber optic transceivers by three sets of performance criteria: transceiver, receiver, and transmitter. Clock recovery, a product feature, can also be specified for high-speed serial data streams... Search by Specification | Learn More
  • Network and Communication Chips-Image
    Network and Communication Chips - (406 companies)
    ...devices, protectors, receivers, repeaters, radio frequency identification (RFID) devices, sample rate converters, serializers-deserializers (SerDes), subscriber line interface circuits (SLIC), storage interfaces, transmitters, transceivers... Search by Specification | Learn More
  • Fiber Optic Receivers-Image
    Fiber Optic Receivers - (126 companies)
    ...by a fiber optic transmitter (or transceiver) and travels along single-mode or multi-mode optical cable, depending on device capabilities. A data demodulator converts the light signal back into its original electrical form. In more complex fiber optic... Search by Specification | Learn More
  • IP Cores - (121 companies)
    Intellectual property (IP) cores are pre-designed, pre-tested, integrated circuits or boards of industry-standard functions that can be easily used in embedded applications. Generally IP cores are treated as intellectual property and are licensed to OEMs. Search by Specification | Learn More
  • IC Interfaces - (510 companies)
    ...transceiver logic (GTL), and gunning transceiver logic plus (GTLP); emitter coupling logic (ECL), positive ECL (PECL), and low-voltage PECL (LVPEC); low-voltage differential signaling (LVDS), bus LVDS (BLVDS), and multi-point LVDS (M-LVDS); digital visual... Search by Specification | Learn More
  • RF Modules - (142 companies)
    ...and transceivers. RF modules use several different modulation methods and radio techniques. On-off key (OOK) modulation turns a signal on or off. Amplitude modulation (AM) causes the baseband signal to vary the amplitude or height of the carrier wave... Search by Specification | Learn More
  • Fibre Channel Connectors - (24 companies)
    ...connectors fit together in only one way. Gigabit interface converters (GBIC) are transceivers that convert between serial-electrical and serial-optical signals for high-speed networking. They are used with both Fibre Channel and Gigabit Ethernet networks... Search by Specification | Learn More
  • Fiber Optic Transmitters - (123 companies)
    Fiber optic transmitters are devices that include an LED or laser source, and signal conditioning electronics, to inject a signal into fiber. Search by Specification | Learn More
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Product News for 40 Gbps SerDes For Transceiver

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More Information on: 40 Gbps SerDes For Transceiver

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  • Altera Provides 50-Gbps SFI-5 Interface on Stratix II GX FPGAs
    San Jose, Calif. -- January 23, 2008 -- Altera Corporation today announced SERDES Framer Interface Level 5 (SFI-5) standard support in its Stratix® II GX FPGAs with embedded transceivers , providing a 40 - to 50- Gbps interface for high-performance optical communications applications.
  • A selt-testing BOST for high-frequency PLLs, DLLs, and SerDes
    The number of pins for SerDes parallel ports is typically 8 or 10 bits for <3 Gbps, 16 or 20 bits for 2~5 Gbps, 32 or 40 bits for 4~10 Gbps , and 64 or 80 bits for >9 Gbps. The smallest SerDes FPGAs have over 350 signal pins, which permits full parallel and serial access to a DUT with 8 transceivers having 8- or 10-bit ports, 4 transceivers that have 16- or 20- bit ports, or 2 transceivers with 32...
  • Fujitsu Launches Second Generation Ultra-fast 65GSa/s 8-Bit ADC Technology f...
    ...to smaller process nodes enables greater functionality in the DSP and a roadmap for smaller form factors... For the design of single-die transceiver SoCs in 40 nm, the Fujitsu IP offering includes high speed 11 Gbps SerDes , supporting a range of protocols and data rates, and will also include a complementary high speed 55 - 65GSa/s 8-bit DAC.
  • Luminent selects Mindspeed’s SerDes transceivers
    ...SerDes transceivers in production today can only handle speeds up to 2.125 Gbps in multi-channel... The pairing of Luminent's CWDM products and Mindspeed Technologies' SerDes transceivers provides optical-networking equipment manufacturers with a timely, cost effective and seamless solution for supporting up to 40 km 10 Gigabit Ethernet physical layer implementations. The proven combination will enable manufacturers to satisfy the rapidly increasing demand for greater bandwidth build-outs...
  • 40-Gbps Sonet/SDH IP cores
    • Avago Technologies First to 28- Gbps Performance with 40 -nm SerDes • Altera Ships Arria II GX FPGAs: High-Performance, Low-Cost Transceiver FPGAs for 3-Gbps Applications .
  • LEDA Systems Announces Family of Advanced Serial Transceiver Semiconductor I...
    This exceeds requirements for optical standard OC-768 and for the Optical Networking Forum's SerDes Framer Interface specification -- SFI-5 -- that supports data rates of up to 40 Gbps in each direction. LaSer Serial Link Transceivers are currently implemented in 0.18 micron, 0.15 micron and 0.13...
  • Semiconductor intellectual property and system-on-chip for communications the future for small companies
    competitive serializerldesenalizer (SerDes) IP products, and can be easily integratedon system-on-a-chip(SOC) designs. SERDES . Typical requirements: 10 Gbps Serial Link Transceiver ; LVDS and CML based Transceiver technology: 16 channels of 622 Mb/s; 8 channels of 1.25 GB/s: 4 channels of 3.125 GB/s: 2 channels of 5.0 GB/s; 40 Gbps Serial Link Transceiver; CML... Selection Criteria for the IP usually are: Smaller Die size, Type of CDR technology (the size matters...
  • A parallel multi-pattern PRBS generator and BER tester for 40/sup +/ Gbps Serdes applications
    This paper presents the design of a low cost PRBS generator and a BER tester for up to 40 + Gbps Serdes applications. All the circuit blocks are designed using a 0.18 pm CMOS technology for system integration with... transceivers [4][5][6].
  • Analog Circuit Design
    Song Wu, et al., “Design of a 6.25- Gbps Backplane SerDes with Top-Down Methodology�?, Design and test for multiple Gbps communication devices and systems, IEC 2005, p. 283. R. Payne, et al., “A 6.25-Gb/s binary transceiver in 0.13 μm CMOS for serial... IEEE JSSC, Vol. 40 , No. 12, December 2005, pp. 2646–2657.
  • ATLAS LAr calorimeters readout electronics upgrade R&D for sLHC
    They use commercial parallel optical transceiver running at 75 Gbps with MPO /MTP low profile connector, SERDES of Xilinx Virtex-5 FPGA and Altera Stratix II GX FPGA are tested successfully. The feasibility of fast and large volume data preparation within fixed latency budget for Level-0 and... The data volume is expected to be 40 Tbps for L0Calo processing and 2Tbps for L1Calo processing.
  • Monolithically integrated high-speed CMOS photonic transceivers
    [1] S. Bates and K. Iniweski, “10 Gbps over copper lines-state of the art in VLS... Workship on System-on-Chip for Real-Time Applications, pp. 491-494, 2005 [2] T. Beukema, M. Sorna, K. Selander, S... ...W. Rhee, H. Ainspan, B. Parker, and M. Beaks, “A 6.4-Bg.s CMOS SerDes core with feed-forward... 40 , pp. 2633-2645, Dec. 2005 [3] G. Masini, G. Capellini, J. Witzens, and C. Gunn, “High-speed, monolithic... ...photodetectors,�? Proc. LEOS 2007, pp. 848-849, Oct. 2007 [4] A. Narasimha, “A 40-Gb/s QSFP optoelectronic transceiver in a 0.13μm...
  • NurLogic Delivers Quad 3.318 Gbps SerDes Transceiver Cores Offering The Indu...
    • NurLogic announces Silicon Validation of its Quad 3.125 gbps SerDes Transceiver IP Cores • Altera Ships Arria II GX FPGAs: High-Performance, Low-Cost Transceiver FPGAs for 3-Gbps Applications • Lattice Delivers Flexible, Programmable 40 Gbps Serdes Framer Interface, Level 5 (SFI5) IP Core Solution .
  • ADC-based serial I/O receivers
    Sahn, et al., "A 2.2 Gbps CMOS look-ahead DFE receiver for multidrop channel with pin-to-pin time... ...in a dual-mode (PAM2/4) serial link transceiver �?, 2004 VLSI Symp... ...al., “A 12.5Gb/s SerDes in 65nm CMOS Using... ...CMOS,�? 2006 CICC, pp. 489-92 [16] S. Galal, B. Razavi, “ 40 -Gb/s amplifier and...
  • Data link design using a time-based approach
    Abstract—A time-based approach to SerDes data transfer is described. As proof of concept, 2-bit 800 Mbps and 3-bit 1.2 Gbps time-based serial links have been designed and implemented using an Altera transceiver signal integrity development FPGA kit. The eye diagram of both the transmitted signal and the signal at the end of a 40 -inch FR4 trace have been measured and compared for both links.
  • A 4.8-6.4-Gb/s serial link for backplane applications using decision feedback equalization
    ...design that is capable of 4.8–6.4-Gb/s binary NRZ signaling across 40 of FR4 copper... The transmitter fea- tures a programmable two-tap feed forward equalizer and the re- ceiver uses an adaptive four-tap decision feedback equalization to compensate for the losses in the channel at 6.4 Gbps . The trans- ceiver core is built in LSI’s 0.13- m standard CMOS technology to be integrated into ASIC designs that require serial links. Index Terms—Adaptive equalization, backplane transceiver, de- cision feedback equalization (DFE), SerDes , serial link.