Supplier: American Microsemiconductor, Inc.
Description: 2-Way Set Associative 4kx18
- Memory Category: SRAM
- IC Package Type: Other
- Logic Family: CMOS 4000
- Supply Voltage: 5 V
Description: including several backpropagation schemes, creeping random search, competitive learning with and without adaptive-resonance function and "conscience," counterpropagation, nonlinear Grossberg-type neurons, Hopfield-type and bidirectional associative memories, predictors, function learning
Description: /Cache [2-Way Set-Associative, Flexible Allocation] • 4.75M-Bit (608K-Byte) L2 Unified Mapped RAM/Cache [4-Way Set-Associative, Flexible Allocation] • L1P Memory Controller • L1D Memory Controller • L2 Memory Controller – Time Stamp Counter – One 64-Bit
Description: core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 32KB direct mapped cache and the Level 1 data cache (L1D) is a 32KB 2-way set-associative cache. The Level 2 program cache (L2P) consists of a 128KB memory space that is shared between program and data space. L2
Digital Signal Processors (DSP) - Texas Instruments OMAP-L132 C6-Integra DSP+ARM® -- 595-OMAPL132BZWT2Supplier: Mouser Electronics, Inc.
Description: or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The device DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 32KB direct mapped cache and the Level 1 data cache (L1D) is a 32KB 2-way set-associative cache. The Level 2 program cache (L2P) consists
- Data Bus: 32-Bit
- Supply Voltage: 1.8 V
- Package Type: BGA
- Interfaces: UART
Find Suppliers by Category Top
Conduct Research Top
Machine Vision Systems in the Dutch Orchid Industry - A Flower Power Success
applications and for many purposes. develop innovative vision software. Their fascination with. such as automatic quality control, measurement, identifica-. pattern recognition and associative memory helped them. tion, or monitoring. create one of the finest color segmentation algorithms
Interface Solutions for Planar's EL Displays
functionality of the device is built around. an ARM720T processor with 8 Kbytes of four-way set-associative unified cache. and a write buffer. http://www.cirrus.com/en/products/pro/detail/P139.html. Sharp LH7A404 (supports 4 and 8 bit interface products). The LH7A404 microprocessor, powered
Implement High-Performance Floating-Point Processing on FPGAs
. The reason is that floating-point operations are not associative, which. can be proved easily by writing a program in C or MATLAB to sum up a selection of. floating-point numbers. Summing the same set of numbers in the opposite order will. result in a few different LSBs. To verify the floating-point
Engineering Web Search: Associative Memory Top
CPU cache - Wikipedia, the free encyclopedia
As long as most memory accesses are cached memory locations, the average latency of memory accesses will be closer to the cache latency than to the
Translation lookaside buffer - Wikipedia, the free...
A translation lookaside buffer (TLB) is a cache that memory management hardware uses to improve virtual address translation speed.
CiteULike: Group: NeuralNetworks - with tag...
Group: NeuralNetworks - with tag associative-memory [4 articles
"" Linux on Memory Card "NetBSD" netbsd "" 203 /dev/hda1 "" NetBSD on Memory Card "RedBoot" redboot "" 203 /dev/hda1 "" RedBoot on Memory Card
SPARC JPS1 Implementation Supplement
Traps 39 8. Memory Models 41 Overview 42 SPARC V9 Memory Model 42 Mode Control 42 Synchronizing Instruction and Data Memory 42 A. Instruction
PHP: Description of core php.ini directives - Manual
memory_limit integer This sets the maximum amount of memory in bytes that a script is allowed to allocate.
PHP: PHP 4 ChangeLog
Fixed MOPB-24-2007 (Fixed unallocated memory access/double free in in array_user_key_compare()). Fixed bug #40611 (possible cURL memory error).
Natural Language through Abstract Memory
In the superstructure model for natural language, an "abstract" memory channel is superimposed to flow in parallel with the input/output channels, in
Using Cache Memory on Blackfin? Processors Application Note...
VisualDSP++? Compiler Support............................... 28 Cache Memory Concepts ....................................................3 Header
Cortex-A9 Processor - ARM
Embedded Memory IP Interface IP POP??? IP Memory Controllers CoreSight More System IP