Associative Memory

Description: 2-Way Set Associative 4kx18

• Memory Category: SRAM
• IC Package Type: Other
• Logic Family: CMOS 4000
• Supply Voltage: 5 V

Description: including several backpropagation schemes, creeping random search, competitive learning with and without adaptive-resonance function and "conscience," counterpropagation, nonlinear Grossberg-type neurons, Hopfield-type and bidirectional associative memories, predictors, function learning

Description: /Cache [2-Way Set-Associative, Flexible Allocation] • 4.75M-Bit (608K-Byte) L2 Unified Mapped RAM/Cache [4-Way Set-Associative, Flexible Allocation] • L1P Memory Controller • L1D Memory Controller • L2 Memory Controller – Time Stamp Counter – One 64-Bit

Description: core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 32KB direct mapped cache and the Level 1 data cache (L1D) is a 32KB 2-way set-associative cache. The Level 2 program cache (L2P) consists of a 128KB memory space that is shared between program and data space. L2

Description: or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The device DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 32KB direct mapped cache and the Level 1 data cache (L1D) is a 32KB 2-way set-associative cache. The Level 2 program cache (L2P) consists

• Data Bus: 32-Bit
• Supply Voltage: 1.8 V
• Package Type: BGA
• Interfaces: UART