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  • MICRO: Breakout
    ISMI program to develop 300 mm Prime, explore transition to 450-mm manufacturing The International Sematech Manufacturing Initiative (ISMI) has started a program to explore critical issues and potential barriers to introducing a new wafer size for IC manufacturing. The initiative, begun
  • | Electronics Industry News for EEs & Engineering Managers
    Commentary: Lower test costs start with IC design You can bring test costs under control by starting with IC design, says James Healy, CEO of LogicVision. But organizational barriers are formidable, he notes. Bristol group gets grant to develop video over wireless Wireless video specialist
  • MICRO: Product Extras (Jan '2000)
    A system for measuring copper CMP process parameters on-line in the polisher has been developed by Based on the company's NovaScan technique, the system measures metal loss, metal thickness, and residues inside the die on actual structures. The technology will enable IC manufacturers to shift
  • MICRO: The Hot Button
    distinguished chair of microelectronics in the department of electrical engineering and computer sciences at the University of California, Berkeley. The award-winning educator is a prolific researcher and technical-paper writer, and is recognized as one of the foremost experts in FinFETs and IC
  • High-Voltage ICs
    types to be affected will be low-current versions in nonisolated applications. A high-voltage IC process is credited for the first major change in low-power supplies in 20 years. Single-chip supplies were, in the past, not feasible because breakdown-voltage barriers prevented conventional ICs from
  • MICRO:Defect Inspection Equipment, by Thomas Reuter (Oct '99)
    to determine the AIT II's production worthiness, its applicability to IC production, and its advantages over its predecessor, the AIT I. During the study, inspection recipes were created for a range of IC products. The article summarizes data collected from 64- and 256-Mb memory applications, including
  • | Electronics Industry News for EEs & Engineering Managers
    . barrier Cypress, Mosel Vitelic to develop 0.13-micron process technology ESEC develops flexible die bonder for wider range of IC packages Taiwan's government delays S3-Via venture in graphics chips Silicon Genesis expands SOI wafer manufacturing capacity, ships samples 'E-diagnostics' heats up
  • MICRO: Materials Integration
    Stephen Savas, Rene George, and David Gilbert, ; John Cain, Matthew Herrick, and Andy Nagy, ; and Kumar Karuppana, formerly of he successful integration of copper interconnects and low-k dielectrics in dual-damascene processes has been a critical, but difficult, step in the development of IC

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