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  • MICRO: Product Extras (Jan '2000)
    A system for measuring copper CMP process parameters on-line in the polisher has been developed by Based on the company's NovaScan technique, the system measures metal loss, metal thickness, and residues inside the die on actual structures. The technology will enable IC manufacturers to shift
  • EETimes.com | Electronics Industry News for EEs & Engineering Managers
    . barrier Cypress, Mosel Vitelic to develop 0.13-micron process technology ESEC develops flexible die bonder for wider range of IC packages Taiwan's government delays S3-Via venture in graphics chips Silicon Genesis expands SOI wafer manufacturing capacity, ships samples 'E-diagnostics' heats up
  • MICRO: Special Apps
    Paul Werbaneth, Tegal; and Tim Lester and Jadwiga Pakulska, Nortel Networks A variety of metals can be used for interconnect metallization in IC and MEMS device fabrication. Aluminum and aluminum alloys, tungsten, copper, platinum, and gold are all employed as thin-film conductors
  • MICRO: Materials Integration
    Stephen Savas, Rene George, and David Gilbert, ; John Cain, Matthew Herrick, and Andy Nagy, ; and Kumar Karuppana, formerly of he successful integration of copper interconnects and low-k dielectrics in dual-damascene processes has been a critical, but difficult, step in the development of IC
  • MICRO:Defect Inspection Equipment, by Thomas Reuter (Oct '99)
    to determine the AIT II's production worthiness, its applicability to IC production, and its advantages over its predecessor, the AIT I. During the study, inspection recipes were created for a range of IC products. The article summarizes data collected from 64- and 256-Mb memory applications, including
  • MICRO: Defect/Yield Analysis & Metrology
    A joint study reveals that optoacoustic metrology can be used to optimize chemical-mechanical planarization processes and track film-thickness variations during production. ith the IC industry rapidly switching to copper for circuit interconnects, the lack of etching techniques to remove copper has
  • MICRO: Building Copperopolis II by Israel Ybarra Jr. (Jan 2000)
    and Gaurav Virendra Gupta, A spin-process technique prevents back-surface particle contamination of the process chuck, creates an edge exclusion zone, and optimizes the copper/barrier material interface. s device features shrink below 180 nm, interconnect delay becomes critical, making

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