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Supplier: PLX Technology, Inc.
Description: PCI BUS CONTROLLER, PBGA176
- Supply Voltage: 1.2 V
- IC Package Type: Other
- Features: RoHS Compliant
- Device Type / Applications: Line / Bus Controller
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IC Bus Interfaces and Controllers (112 Companies)
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Supervisory Control and Data Acquisition Systems (SCADA) (424 Companies)
Featured Products for Bus Master Top
Crane Aerospace & Electronics
VME Master Oscillator
function provides indication, through the VME bus, of the signal output presence for each output. Also provided is the ability to disable each output from the command bus. The device is fully tested and guaranteed over the operating conditions. Features. 4 Different Output Frequencies. Internal High-Stability Crystal Reference. Built-in Test Functions... (read more)
Browse Oscillators Datasheets for Crane Aerospace & Electronics
CONTEC Co., Ltd.
High Speed Analog w/Simultaneous Sampling
software. EXTERNAL STATUS OUTPUT SIGNAL. LVTTL level - Sampling clock output. BUS MASTER. DMA CHANNELS. 1ch. TRANSFER BUS WIDTH. 32bit. TRANSFER DATA LENGTH. 8 PCI Words (max). FIFO. 1K-word. SCATTER / GATHER FUNCTION. 64M-Byte. SYNCHRONIZATION BUS. CONTROL OUTPUT SIGNAL. Selected via software when specifying a sync master board. CONTROL INPUT SIGNAL. Sync factor selected via software when specifying slave boards. CONNECTORS (CN3, CN4). 2x PS-10PE-D4LI-B1 (mfg by JAE) or equivalent. GENERAL. DIGITAL... (read more)
Browse Data Input Modules Datasheets for CONTEC Co., Ltd.
Parts by Number for Bus Master Top
|Part #||Distributor||Manufacturer||Product Category||Description|
|MLX LIN MASTER||Digi-Key||Melexis Technologies NV||Programmers, Development Systems||LIN MASTER FOR BUS-PC USB CONN|
|1827030151||PLC Radwell||Bosch||Not Provided||ASI BUS MASTER MODULE|
|DS1481S/T&R||Digi-Key||Maxim Integrated||Integrated Circuits (ICs)||IC BUS MASTER 1 WIRE 14-SOIC|
|IC677PBI001||PLC Radwell||Ge Fanuc||Not Provided||PROFIBUS VERSAMAX IP MODULAR LOCAL BUS MASTER WITH|
|PCI 9080-3 G||ASAP Semiconductor||PLZ||Not Provided||PCI BUS MASTER I/O ACCELERATOR CHIP 208PQFP|
|PCI 9656-BA66BI G||ASAP Semiconductor||PLZ||Not Provided||64-BIT; 66MHZ PCI BUS MASTER I/O ACCELERATOR|
Conduct Research Top
Software Implementation of I²C Bus Master
and the user is assumed to have an understanding of the I 2 C Bus. For detailed information on the bus, the user is advised to read the I 2 C Bus Specification document from Philips/Signetics (order number 98-8080-575). The I 2 C Bus is a two-wire serial bus with multiple possible masters and multiple
Use of the SSP Module in the IIC Multi-Master Environment
is the Master (generates the clock and the handshaking signals), while all the other devices are Slaves. The current bus Master can both read-from and write-to any of the Slave units by addressing them individually. On a Multi-Mas-ter bus the Masters follow an arbitration scheme to ensure that the bus
Communicating with IIC Bus Using PIC16C5X
to commu-. logical `1' represents a request for data READ. A data. nicate a microcontroller with a 2-wire bus Serial EEPROM. transfer is always terminated by a STOP condition. through a general purpose I/O port. generated by the master controller. However, if a master. Unlike the 3-wire bus Serial
Safety Products with Integrated Bus Interface
to its. in this case, it can easily be incorporated in the higher-level bus. simple structure, AS-Interface does not require any programming. by means of a gateway. The gateway can also function. For most bus subscribers, in particular safety devices, it is only. simultaneously as the master
VersaModule Eurocard Bus (VMEbus)
as the electronic specifications for sub-bus structures, signal functions, timing, signal voltage levels, and master/slave configurations. The VMEbus uses 3U and 6U Eurocard, rugged circuit boards that provide a 96-pin plug instead of an edge connector for durability. Several VMEbus varieties are available.
AS-interface(R) Simple, Robust, Device-Level Bus (.pdf)
wires of the cable being soldered or crimped to gold-plated brass pins and. sleeves at the factory. 1.1. v2.0 and v2.1. Bus type. Master-to-slave, single master. Bus topology. Free form, unrestricted branching. Physical distance on a single signal. 100 meters. segment. Physical distance with 2
Which bus, when?
It's now easier to see which kind of industrial bus best serves particular industries and applications. Connectors from Lumberg Inc., Midlothian, Va., are tailored for industrial Ethernet. The hybrid design combines an RJ45 electrical connection with the common M12/M18 shell, and protects against
Interfacing PIC18 MCUs with UNI/O(TM) Bus-Compatible Serial EEPROMs
the hardware schematic for the. able I/O. Such restrictions can potentially stem from. interface between the Microchip 11XXX series of. connectors, board space, or from the master device. UNI/O bus-compatible serial EEPROMs and the. itself. PIC18F1220 microcontroller. The schematics show the. The 11XXX
Engineering Web Search: Bus Master Top
64-Bit PCI Master/Target Interface
Includes both bus master and bus target functions The 64-bit PCI master/target megafunction contains the functions of a bus master and a bus target.
32-Bit & 64-Bit Target-Only & Master/Target Interface...
32-Bit & 64-Bit Target-Only & Master/Target Interface Function for PCI Bus & other PCI-Based Standards (CardBus, CompactPCI)
1-Wire - Wikipedia, the free encyclopedia
The master initiates activity on the bus, simplifying the avoidance of collisions on the bus.
IÂ²C - Wikipedia, the free encyclopedia
The bus is a multi-master bus which means any number of master nodes can be present.
- Xilinx DS449 LogiCORE IP Fast Simplex Link (FSL) Bus (v2.11c),...
Xilinx DS402 LogiCORE IP On-Chip Peripheral Bus V2.0 with OPB...
The bus interconnect in the OPB Family (1) -3A DSP V2.0 specification is a distributed multiplexer Resources Used See Table 7. implemented as an AND
DS18B20 is powered by an external supply, the master can issue ???read time slots??? (see the 1-Wire Bus System section) after the Convert T command
This protocol defines bus transactions in terms of the bus state during specified time slots that are initiated on the fal ing edge of sync pulses