Clock Multiplier Chip

Description: Status: ACTIVE The CDCE949 is a modular PLL-based low-cost high-performance programmable clock synthesizer, multiplier, and divider. It generates up to 9 output clocks from a single input frequency. Each output can be programmed in-system for any clock frequency up to 230 MHz, using up to four

Description: (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle Load-Store Architecture With Non-Aligned Support 64

Description: 500 MSPS Selectable 2×-8× Interpolation On-Chip PLL/VCO Clock Multiplier Full IQ Compensation Including Offset, Gain, and Phase Flexible Input Options: FIFO With Latch on External or Internal Clock Even/Odd Multiplexed Input Single Port Demultiplexed Input Complex

• Interface Type: Parallel
• Architecture: Current-Steering
• Output Type: Current
• IC Package Type: Other

Description: 4K Data/8K Instr Cache;MMU;Multiplier

• Architecture: RISC
• Data Bus: 32-Bit
• Package Type: QFP

Description: Status: ACTIVE The CDCE937 and CDCEL937 are modular PLL-based low-cost high-performance programmable clock synthesizers, multipliers, and dividers. It generates up to seven output clocks from a single input frequency. Each output can be programmed in-system for any clock frequency up to 230 MHz

Description: Off Mode (RAM Retention): 0.1 µA Ultrafast Wake-Up From Standby Mode in Less Than 1 µs 16-Bit RISC Architecture, 62.5-ns Instruction Cycle Time Hardware Multiplier Basic Clock Module Configurations: Internal Frequencies up to 16 MHz With Four Calibrated Frequencies to ±1% Internal Very Low