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  • A VHDL Model of a IEEE1451.2 Smart Sensor: Characterization and Applications
    Both these C- based STIMs have an external frequency counter that is realized with an additional small CPLD (64 macrocells used), because considered microcontrollers have internal counters that can operate up to 2.5 MHz (PIC16C62) or 5 MHz (PIC18F452), Power consumption...
  • VHDL implementation of a IEEE1451.2 smart sensor
    Because considered microconhollers have internal counters that can operate up to 2.5 MHz (PIC16C62) or 5 MHz (PIC18F452), both these pC- based STIMs have an external frequency counter that is realized with an additional small CPLD (64 macrocells used).
  • A short time measurement based on length vernier
    ...Chinese Metrology Publish House, 1996 [2] HP5370B Universal Time Interval Counter Manual [3] Wei Zhou... ...time interval measurement technique based on time – space... ...processing, 2006 IEEE International Frequency Control Symposium [4] Wei... ...Interval Measurement Based on CPLD , Measurement Technique, No. 7...
  • A Designer’s Guide to Built-In Self-Test
    ...clique partitioning algorithm 126 clock enable problem 119, 206 clock frequency 12 clock-to-output... ...11, 82, 84 comparator- based ORA 82, 111, 226... ...Complex Programmable Logic Device ( CPLD ) 32, 53,193, 221... ...223, 242 constant-weight counter 63 controllability 33, 43...
  • Using FPGA and CPLD ICs to Achieve High-Frequency PWM
    This paper is the development of a high- frequency PWM generator architecture for power converter control using FPGA and CPLD ICs. The proposed architecture is based on a special design synchronous binary counter and can be easily interfaced to a microcontroller or DSP system.
  • Design and application of digital servo controller module based on DSP and CPLD
    The time- base of internal QEP unit provided by the LF2407A interior timer reaches 20MHz. Here, two channels QEP maximum sampling frequency of encoder is 20MHz, and the units in DSP internal inherent were used to connect two channels encoder’s signals, and another two channels encoder’s signals connected with DSP by CPLD decoding interface[5]. The CPLD counter bit can be setup voluntarily, and the frequency reaches to hundred megahertz.
  • The Development of Automatic Electronic Granulation Counter Based on Mechanical Properties
    The counter consists of LED light source, double linear array CCD sensors TCD1209D, synchronously driving circuit for double linear array CCD based on CPLD EPM3064A, synchronously data acquisition card with A/D converter TLC 5510 of the high speed, and host computer. 400 millimeter wide, the horizontal resolution is 0.1 millimeter, the driving frequency of linear array... The experiments show the electronic granulation counter is accurate and reliable, counting speed is over 8000 per...
  • A high performance frequency insensitive quadrature phase shifter and its application in reactive power measurements
    The frequency insensitive quadrature phase shifter was built using an 18-bit h4DAC. an 18-bit counter and control logic implemented in an in-system programmable CPLD and a reference oscillator allowing operation in the wide frequency range of 45 Hz to... 1 ~ ~ The presented design approach for precision reactive power measurements is based on the frequency...
  • A multichannel photon counting system for gas analysis with Raman-scattering technique
    One part of the schematic diagram of the as above CPLD - based counter is presented in Fig. 3 for the ULD counter. These counters are used to divide an incoming clock frequency and, thereby, provide a new clock to...
  • Power Aware Remote Information System (PARIS)
    Table 4 shows an example of a 32-bit counter implementation on a CPLD and multiple implementations on FPGAs. The speed of CPLD based counters is independent of counter size. Device Type # Cells (% of Device) Maximum Frequency .
  • CPLD-based system for the quadrature digital upconverter
    THE FORMER OF FREQUENCIES CPLD-based system meant for the clocking frequency formation equal to 20 kHz... The second variant provides the project implementation in any CPLDs , FPGAs, SoCs and others. The being presented IP-CORE consists of counters and triggers based on components from the library lpm.
  • The Phase Stabilities of the Servo Circuit in a Rubidium Vapor Cell Frequency Standard
    phase shifter based on CPLD is proposed. Figure 4:The block diagram of a digital phase shifter As shown in Figure 4, fre1 and fre2 are the frequency division of VCXO by using a same counter , and the phase between fre1 and fre2 can be adjusted through modifying the value...
  • Digitally controlled point of load converter with very fast transient response
    Compared to a more traditional digital PWM modulator based on a counter and comparator the DiSOM modulator allows the sampling frequency of the output voltage control loop to be higher than the switching frequency of the power converter, typically a DC/DC converter. combined with a digital PID compensator algorithm is implemented in a hybrid CPLD /FPGA and is...
  • Design of High-Precision Frequency Measure System Based on CPLD Time Delay Unit
    In real design, using VCXO to generate 16.384M frequency standard, using GPS module Navman JUPITER 21... FIG.2 Functional block diagram of the high precision of measurement by the method of quantization time-delay based on CPLD . ...key element of the design is the logic and time design, including direct counter , time interval measuring...