Supplier: American Microsemiconductor, Inc.
Description: Multiple clocks
- Product Terms per Macrocell: 68
- IC Package Type: Other
- Logic Family: Standard CMOS / CMOS 4000
- Pin Count: 28
Supplier: 1-Source Electronic Components
Description: IC, CPLD, FLASH, 1700, 7NS, 304MHZ, BGA-324 CPLD Type:FLASH No. of Macrocells:1700 No. of I/Os:272 Series:MAX II Propagation Delay:7ns Global Clock Setup Time:1.2ns Frequency:304MHz RoHS Compliant: Yes
- Macrocells: 1700
- Internal Frequency: 3.04E8 Hz
- User I/Os: 272 pins
- Propagation Delay: 7 ns
Supplier: 1-Source Electronic Components
Description: CPLD IC, EEPROM, 128, 10ns, 98MHz, 100-TQFP CPLD Type:EEPROM No. of Macrocells:128 No. of I/Os:80 Series:MAX 3000A Propagation Delay:10ns Global Clock Setup Time:6.6ns Frequency:98MHz Supply Voltage Range:3V to 3.6V RoHS Compliant: Yes
Supplier: Precise Time and Frequency, Inc.
Description: requiring sub-microsecond timing. The microprocessor/CPLD combination performs both the GPS navigation and oscillator disciplining functions. The GPS receiver is driven directly by the 10MHz output signal of the oscillator. This is calibrated against the incoming GPS signal, with the resulting clock
- Clock method: Crystal, External Signal
- Interface: Serial, Status Indicators, Other Interface
- Outputs: 1pps, 10MHz
- Number of outputs: 12
Supplier: Aaeon Systems Inc.
Description: The PFM-C20N sells with the option to have either PC/104 or PCI-104 expansion interfaces and uses the NXP Semiconductor SJA 1000 chipset for CAN2.0 support with speeds of up to 1MBps. The PFM-C20N includes options for setting the IRQ's for CAN buses as well as setting the PCI clock
- Product Type: Bus Interface / Adapter Module
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mPlatform: A Reconfigurable Architecture and Efficient Data Sharing Mechanism for Modular Sensor Nodes
CPLD clock cycles are required to transfer a data packet from the Besides unicast and broadcast transmission of data packets, the .
Cyclops: In situ image sensing and interpretation in wireless sensor networks
CPLD clock control .
PM73122 | Datasheets.org.uk
RSTB inout std_logic; CPLD clock : LCLK_CPLD std_logic; output signals: CHIP_ADDRESS std_logic_vector(19 downto (others 'Z') CHIPADgeneration; architecture CHIPADgeneration CHIPADgeneration signal std_logic; signal std_logic; begin process(LCLK_CPLD, L_ADSB, L_ALE, L_DT_RB, L_DENB) begin (LCLK_CPLD'event LCLK_CPLD '1') then (L_ADSB L_ALE L_BLASTB L_DENB '1') then CHIP_ADDRESS...
February 2010 Copyright 2010 Altera Corporation. rights reserved. | Datasheets.org.uk
oscillator oscillator oscillator (for CPLD ) Clock input SMAs Clock output CLKIN_P (positive) CLKIN_N (negative .
Tsi109 | Datasheets.org.uk
GPIO8, GPIO9, GPIO10, GPIO11, GPIO12, GPIO13, GPIO14, GPIO15 CPLD Clock implemented this time input OSC25_CPLD_CLK; Reset Directions input output BOARD_RESETn; output MEMORY_RESETn; output HRESET_750n; output SRESET_750n; Data Retry Directions output DRTRY_750n; Directions parameter PCIX133 parameter PCIX66 parameter PCI66 parameter PCI33 input XCAPMSB...
CPLD clock can be halted when it is not required by the MCU in order to minimize the power consumption.
GPS Time Synchronization in School-Network Cosmic Ray Detectors
Thus the timing resolution is 24 nanoseconds, and with 32-bit register width, the CPLD clock counter rolls over every 103 seconds.
GPS time synchronization in school-network cosmic ray detectors
Thus, the timing resolution is 24 nanoseconds, and with 32-bit register width, the CPLD clock counter rolls over every 103 seconds.
PowerPC 750GX/GL Evaluation Board User's Manual January 2006 | Datasheets.org.uk
CPLD Clock implemented this time input CPLD_CLK; .
Dynamic Digital Optical Tomography for Cancer Imaging and Therapy Monitoring
t_cnvst must be at least 1.75 µs and t_read_clk is dictated by the CPLD clock , which is 30 MHz, .
Both of these systems are clocked from the main CPLD clock .
Personal digital assistant (PDA) based I2C bus analysis
...necessary glue logic that would otherwise be handled by external circuitry, and since it can be powered by the PDA power source, the only other hardware components that are necessary are an oscillator for generating the CPLD clock and external connections for...
A survey of visual sensor network platforms
For example, CPLD clock is halted by the MCU when its services are not required; likewise, SRAM is kept in sleep state when the memory resources are not needed.
Implementation of Micro controller and reconfigurable logic Co-Design for low latency control
The CPLD works on it own frequency of 3.2 MHz but the shift register dose not follow the CPLD clock .
Cypress 39K200 CPLD Clock /Control Network .