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IndustryPack® Modules - Cyclone II FPGA with Digital I/O (JTAG-configured), IP-EP200 Series -- IP-EP201Supplier: Acromag, Inc.
Description: through the JTAG port or via the IP bus directly into the FPGA. A pre-programmed internal CPLD facilitates initialization by acting as the bus controller during power-up and while the program is downloading. This bus controller is limited to functions necessary for power-up and
- Features: Integrated Counter / Timers, Programmable Channels
- IP Bus Width: 8-bit, 16-bit
- IP Clock Rate: 8 MHz, 32 MHz
- IP Module Type: Other
Supplier: Electro Standards Laboratories
Description: Programmable Logic Device). The CPLD is in a 208-pin PQFP package with a standard 10-pin JTAG interface port. The CPLD has 10,000 usable gates, 512 macrocells, 32 logic array blocks and 172 user I/O pins. The CPLD is factory programmed with standard motor control
- Configuration: PC Board
- Features: Brake Output, Auxiliary I/O
- Number of Axes / Motors: 15
- Operating Temperature: 0.0 to 70 C
Description: on pin 14 allows processor reset of Xilinx Zynq platform. â€¢ Xilinx FPGAs,â€¢ Xilinx Zynq-7000,â€¢ Xilinx CoolRunnerâ„¢/CoolRunner-II CPLDs,â€¢ Xilinx Platform Flash ISP configuration PROMs,â€¢ Selected third-party SPI PROMs,â€¢ Selected third-party BPI PROMs For Use With = JTAG-HS3,Show More
Supplier: Atmel Corporation
Description: This document describes in detail the ATF15xx-DK3 CPLD Development/Programmer Board, Adapter Boards and JTAG ISP download cable. It also contains a tutorial describing a complete VHDL design flow using ProChip Designer, ATMISP, and ATF15xx-DK3. Get the VHDL design (F02_44TQFP.VHD) usedShow More
Description: FPGAs. â€¢ Xilinx Zynq-7000. â€¢ Xilinx CoolRunnerâ„¢/CoolRunner-II CPLDs. â€¢ Xilinx Platform Flash ISP configuration PROMs. â€¢ Selected third-party SPI PROMs. â€¢ Selected third-party BPI PROMs For Use With = JTAG-HS3, Xilinx ToolShow More
Description: expansion header landings for I/O and external power. 1 x 8 expansion header landing for JTAG. 4 x 15 hole prototyping area. +3.3 and +1.8V supply rails. Board size: 3in x 3in Classification = Development Kit Technology = CPLDShow More
Description: A complete digital design lab at your fingertips! Equipped with an Altera MAX® II EPM2210F324C3 device and on-board USB Blaster circuit, the MAX II Micro Kit provides users the best and largest CPLD design resource. MAX II Micro board can also be used as a USB Blaster cable (JTAG modeShow More
Supplier: Aaeon Systems Inc.
Description: setup of a Terminating Resistor. In addition to either PC/104 or PCI-104 connectors, the PFM-C20N has one CAN Bus connector and one CPLD JTAG connector. With operating system support of Windows XP and Linux, the PFM-C20N was designed to exploit the benefits of expansion present in
- Product Type: Bus Interface / Adapter Module
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Review of Real-Time Simulator and the Steps Involved for Implementation of a Model from MATLAB/SIMULINK to Real-Time
CPLD JTAG interface: If the ‘‘JUMP4’’ jumpers are set to the independent mode, this connector gives access to the CPLD JTAG configuration interface.
The ATLAS ROBIN
The FPGA can be configured by one of three interfaces: a separate JTAG port7 on the CPLD JTAG connector, a JTAG port emulated by the PCI bridge or a JTAG port emulated by the CPU.
Cube: A 512-FPGA cluster
There are also three pairs of programming headers for CPLD JTAG , FPGA JTAG and FPGA Slave Serial configu- ration.
Simulation and real-time implementation of shunt active filter id-iq control strategy for mitigation of harmonics with different fuzzy membership functions
CPLD JTAG interface 4 .
A Reconfigurable Neural Signal Processor (NSP) for Brain Machine Interfaces
Through these connectors there is access to the CPLD jtag , MSP serial ports, wireless chip, and other general CPLD IO for multiplexing communication between the components of the NSP.
Implementation and evaluation of an OFDM-based MIMO system
Reprogramming is done through the CPLD JTAG port using Altera’s HDL Design Software.
Adaptation of the IEEE 802.15.4 MAC layer to an ultra wide band radiofrequency physical layer
1 :UART 0 2 : CPLD JTAG Port 3 :UART 1 4 RS-232-0port .
Partitioning, predictability, P-terms and pinlocking-understanding the new CPLDs
Currently, most JTAG CPLD support is restricted to BYPASS, EXTEST, SAMPLUPRELOADand Program.
Design of image test signal generator about HDTV based on CPLD
Clock module can stably generate 74.25MHz frequency as the main clock of the CPLD . JTAG module is a socket with ten plug jacks.
Implementing the Top Five Control-Path Applications with Low-Cost, Low-Power CPLDs (.pdf)
This function configures the flash device using JTAG via the CPLD ’s JTAG pins.