|
|
|
|
|
Product Announcements
|
|
Custom Dynamic Seals
SKF/North America Large Diameter Radial Seals SKF/North America V-Rings Daemar Inc. Single Acting Piston Seals Hallite Seals International Ltd. Axial C-Seals - Dynamic Seal JETSEAL, Inc. Airseal Inflatable Seal Trelleborg Sealing Solutions |
|
Voice over IP - Wikipedia, the free encyclopedia These solutions typically allow arbitrary and dynamic interconnection between any two domains on the Internet whenever a user wishes to place a call. |
|
|
ADC16DV160 - Dual Channel, 16-Bit, 160 MSPS Analog-to-Digital... Automatic power-up calibration enables excellent dynamic performance and reduces part-to-part variation, and the ADC16DV160 can be re-calibrated at See National Semiconductor Information |
|
|
RTP: Some Frequently Asked Questions about RTP How is the jitter computed? What is the session bandwidth? |
|
|
Special Publication 800-58 Security Considerations for Voice... |
|
|
Tutorials - Maxim Defining and Testing Dynamic Parameters in High-Speed ADCs, Part 1 Design a Low-Jitter Clock for High-Speed Data Converters See Maxim Integrated Products, Inc. Information |
|
|
Linux Tips command: $ ntpq -pn remote refid st t when poll reach delay offset jitter =================================================== tock.usno.navy 0.0.0.0 |
|
|
Adaptive Clock Recovery Mechanism Having Dynamic Frequency... Adaptive Clock Recovery Mechanism Having Dynamic Frequency Drift and Buffer Level Control in Packet Switched Networks |
|
|
Dynamic frequency tracking and phase error compensation clock... Dynamic frequency tracking and phase error compensation clock de-skew buffer |
|
|
Xilinx UG070 Virtex-4 FPGA User Guide, User Guide See Xilinx, Inc. Information |
|
|
Xilinx DS100 Virtex-5 Family Overview transceivers can be used as PHY or connect to - PLL blocks for input jitter filtering, zero delay buffering, external PHY using many soft MII (Media See Xilinx, Inc. Information |