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Parts by Number Top

Part # Distributor Manufacturer Product Category Description
dsPIC33FJ128MC804 Microchip Technology, Inc. Microchip Technology, Inc. Not Provided . - Integrated signal conditioning. - Slave address masking. . UART (up to two modules): - Interrupt on address bit detect. - Interrupt on UART error. - Wake-up on Start bit from Sleep mode. - 4-character TX and RX FIFO buffers. - LIN bus support. - IrDA ® encoding and decoding in hardware...
dsPIC33FJ128MC802 Microchip Technology, Inc. Microchip Technology, Inc. Not Provided and sampling modes. . I2C ™ : - Full Multi-Master Slave mode support. - 7-bit and 10-bit addressing. - Bus collision detection and arbitration. - Integrated signal conditioning. - Slave address masking. . UART (up to two modules): - Interrupt on address bit detect. - Interrupt on UART error...
dsPIC33FJ64MC804 Microchip Technology, Inc. Microchip Technology, Inc. Not Provided . - Integrated signal conditioning. - Slave address masking. . UART (up to two modules): - Interrupt on address bit detect. - Interrupt on UART error. - Wake-up on Start bit from Sleep mode. - 4-character TX and RX FIFO buffers. - LIN bus support. - IrDA ® encoding and decoding in hardware...

Conduct Research Top

  • Error Correction Code in SoC FPGA-Based
    This paper examines the potential sources and implications of soft errors and a. method implemented by Altera Corporation and Micron Technology to make. embedded systems more resilient to these types of soft errors through error detection. and correction.
  • Error Correction Code in SoC FPGA-Based Memory Systems
    This paper examines the potential sources and implications of soft errors and a. method implemented by Altera Corporation and Micron Technology to make. embedded systems more resilient to these types of soft errors through error detection. and correction.
  • Minimizing Error
    pharma labeling and information publishing is a bit like running a miniature publishing business. The potential for error is high. As technology has become more readily available to help pharmaceutical companies with this task, more drug companies are automating portions of the process to ensure quality
  • Parity
    Parity is an error-detection method for computers. As data moves through a computer (e.g. from the CPU to the main memory), the possibility of errors can occur, particularly in older 386 and 486 machines. Parity error detection was developed to notify the user of any data errors. By adding a single
  • Cyclic Redundancy Code (CRC)
    and subtraction are equivalent in Modulo 2Most of the popular communication protocols, like (R) arithmetic., SDLC, HDLC and Ethernet, employCAN, USB, IrDA CRC for error detection. Now, M + R = GQ, where the checksum is embedded Normally, for the error detection in digital into the message (M + R). Here
  • A CAN Physical Layer Discussion
    (LLC) manages the overload control and notification, message filtering and recovery management functions. The Medium Access Control (MAC) performs the data encapsulation/decapsulation, error detection and control, bit stuffing/destuffing and the serialization and deserialization functions.
  • [Chapter 10] 10.7 Debugging<
    errors. But even with good error detection, it is often difficult to isolate the problem. The techniques for discovering the source of the problem are a modest few and are fairly obvious. Unfortunately, most awk implementations come with no debugging tools or extensions. There are two classes of problems
  • EETimes.com | Electronics Industry News for EEs & Engineering Managers
    surfaced and announced plans to expand what could be considered an unusual business model for semiconductors: the "fabless silicon foundry " service model. Equipment refines soft-error detection in chips The detection of soft errors in silicon chips is attracting attention on several fronts
  • Medical Device Link .
    transmission rate of a wireless network can be estimated using two factors: the volume of data that must be transmitted and the additional overhead that is required by the given protocol to perform error detection and correction. Multipath and interference effects will cause the occasional transmission to need
  • Ethernet Theory of Operation
    (during the inter-frame gap) to denote the end of the frame. FCS Frame Check Sequence: The 4-octet field at the end of an Ethernet frame that holds the error detection checksum for that frame. IP Internet Protocol: Refers either to IPv4 or IPv6. LAN Local Area Network or Large Area Network. MAC Media