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Supplier: Integrated Device Technology
Description: has excellent phase jitter (< 1ps rms) suitable to clock components requiring precise and low-jitter sRIO clock signals. Designed for telecom, networking and industrial application, the 841664I can also drive the high-speed sRIO SerDes clock inputs of communication processors, DSPs, switches
- Device Type: Clock Generator
- Bus Interface / Output Type: Other
- Package / Form Factor: Surface Mount Technology (SMT), TSSOP
- Supply Voltage: 3.3 volts
Description: , such as the SerDes. The transimpedance amplifier is driven by a single +3.3 V power supply. The TGA4864 is manufactured in a reliable high-speed SiGe process that combines excellent performance together with cost-effectiveness.
- Supply Voltage (VS): 3.3 volts
- Supply Current (IS): 0.0750 amps
- Bandwidth: 3.60E10 Hz
- Package Type: Other
Transient Voltage Suppressor Diodes (TVS) - ESD Protection for Low Leakage Requirements -- UltraGuard SeriesSupplier: AVX Corporation
Description: protection solution for high clock speed integrated circuit application, battery operated device, backlit display, medical/instrument application, low voltage power conversion circuits and power supervisory chip sets. In addition, UltraGuard’s low leakage characteristics are also suitable for optic
Supplier: Howard Computers
Description: The TRP10GVP200x/210x is a highly integrated, serial optical transponder module for high-speed, 10Gbit/s data transmission applications. It is ideally suited for 10 GbE datacom (belly-to-belly for high density applications) and storage area network (SAN / NAS) applications based on the IEEE 802.3ae
- Network Equipment Type: Transceiver
- Protocols / Networks: Fibre Channel
- Data Rate: 1.05E7 kbps
Analog-to-Digital Converter (ADC) Chips - ISLA216S2516-Bit, 250MSPS JESD204B High Speed Serial Output ADC -- ISLA216S25Supplier: Techwell, Inc.
Description: Key Features JESD204A/B High Speed Data Interface JESD204A Compliant JESD204B Device Subclass 0 Compliant JESD204B Device Subclass 2 Compatible JESD204 Output Lanes Run up to 4.375Gbps Highly Configurable JESD204 Transmitter Multiple Chip Time Alignment and Deterministic Latency Support
- Resolution: 16 bits
- DNL: 0.2400 LSB
- INL: 16 LSB
- SNR: 75.8 dB
Supplier: ELMA Electronic Inc.
Description: to the next via high speed interconnecting cables, via signals introduced through the J1 fabric connector, or accessed on the J1 fabric connector using the test backplane’s SMA and SATA cable headers. For convenient testing of VPX boards Designed to the latest VITA 46.0 VPX specifications
- Board Function: Active Backplane
- Bus / Standard: Other
- Form Factor: 6U x 340mm (Size C)
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Featured Products for High Speed SerDes Top
Integrated Device Technology
High-speed JESD204B Serial Interface DAC
IDT ’s DACs with JEDEC JESD204B-compliant interfaces are optimized for high-speed signal synthesis applications such as 3/4G wireless infrastructure equipment, high definition video broadcast and cutting edge instrumentation. They feature selectable interpolation ?lters, and up to eight JESD204B lanes serial interface with multiple device synchronization(MDS) capability. Key Features and Benefits: Dual and Quad channel DAC, 16-bit resolution. DAC update rate up to 2.0Gbps... (read more)
Browse Digital-to-Analog Converter (DAC) Chips Datasheets for Integrated Device Technology
Customize a fiber switch to almost any interface.
Use these Small Form-Factor Pluggable (SFP) Optical Transceivers to bring high-speed fiber and copper interfaces to any SFP slot. Because they come with different speeds, connectors, and types of media, they enable you to customize the SFP slot on your Ethernet switch to almost any interface, whether it ’s copper or fiber. Plus, they ’re hot-pluggable enabling you to change SFPs on the fly when your network requirements change. The SFPs are rated for extreme operating temperatures... (read more)
Browse Fiber Optic Transceivers Datasheets for Black Box
Mentor Graphics Corporation
HyperLynx ® Signal Integrity (SI)
HyperLynx® Signal Integrity (SI) generates fast, easy and accurate signal integrity analysis in PCB systems design. HyperLynx SI helps engineers efficiently manage rule exploration, definition and validation, ensuring that engineering intent is fully achieved. The software is tightly integrated from schematic design through final layout verification. It can quickly and accurately resolve typical high-speed design effects including over/undershoot, ringing, crosstalk and timing. Comprehensive... (read more)
Browse Electronic Design Automation (EDA) and Electronic Computer-aided Design Software (ECAD) Datasheets for Mentor Graphics Corporation
Conduct Research Top
Estimating Clock Tree Jitter
system-level margin to reliably meet the application jitter requirements. If this jitter. threshold is exceeded in high-speed SerDes applications, for example, it could have a detrimental impact on the. Bit-Error Rate (BER) of the associated high-speed communications link. By ensuring jitter design
Synchronizing clock sources for Agilent Pattern Generator 70841B
. high-speed serial data and clock. test techniques, performance data. with the ATM standard’s. signals. In turn, these signals are. and suggested layout. requirements serve the designer. converted to 8-bit parallel data by. recommendations for a 622 MBd. well. This reference design’s. the SerDes IC
MicroTCA TM: Compact, Flexible, Economical Shelf Architecture for Telecom Systems (.pdf)
. and supports all of the protocol options defined for AdvancedMC. provides high-speed connectivity for the AdvancedMC modules,. modules, including Gigabit Ethernet, RapidIO, and PCI Express. giving up to eight protocol independent 12.5 Gb/s SERDES based. The MicroTCA backplane provides an I2C-based Integrated
622 MBd ATM/SONET/SDH PHY Reference Design Development
it is converted into high-speed. serial data and clock signals. In turn, the signals are converted to 8-bit parallel data by the. SerDes IC. The 8-bit data is then passed onto the framer IC and processed. The framer. output 16-bit bus is looped-back into the framer, this data is passed back
Advances in Radar Processing (.pdf)
Processing. Introduction. High Performance, Low Power, Space Efficient. Processing. For the past few years, at GE we have seen multifunctional. It is always desirable to have as much processing power as. radar systems which need to perform much more sophisticated,. possible for today’s multifunctional
More Information on: High Speed SerDes Top
High Speed Serdes Devices and Applications
The pin densities of chip packaging technologies have not increased at the same pace as has silicon density, and this has led to a prevalence of High Speed Serdes (HSS) devices as an inherent part of almost any chip design.
Low-Power Programmable Pseudorandom Word Generator and Clock Multiplier Unit for High-Speed SerDes Applications
In summary, a generic PFSR based, programmable PRWG ar- chitecture and a low noise, multiphase CMU are proposed for high speed SerDes applications.
Competitiveness and Technical Challenges of Low Cost Wirebond Packaging for High Speed SerDes Applications in ASICs
Competitiveness and Technical Challenges of Low Cost Wirebond Packaging for High Speed SerDes Applications in ASICs .
An 8 × 8 20 Gbps Reconfigurable Load Balanced TDM Switch IC for High-Speed Networking
In this paper, we propose a load balanced Birkhoff-von Neumann symmetric TDM switch fabric architecture with high speed SERDES interfaces.
A 10th generation 16-core SPARC64 processor for mission-critical UNIX server
Figure 3.8.3: Block diagram of high speed SerDes with 8 TXs, 8 RXs and 2 PLLs feeding the physical coding sub-layer.
Dynamic arbitrary jitter injection method for ≫6.5Gb/s SerDes testing
However, the AWG must have a high enough sampling rate, several tens of GHz for high speed SerDes testing.
Survey of design and process failure modes for high-speed SerDes in nanometer CMOS
 G. Hetherington and R. Simpson, “Circular BIST testing the digital logic within a high speed Serdes ,�? Proc.
A 6.25 Gbps CMOS 10 B/8 B decoder with pipelined architecture
In the future, this decoder will be integrated into a high speed SerDes . . References .
LogicVision and DA-Test Collaborate to Provide Low Cost High Speed SerDes I/...
LogicVision and DA-Test Collaborate to Provide Low Cost High Speed SerDes I/O Test .
LogicVision Announces Breakthough High-Speed I/O Test Technology
• LogicVision and DA-Test Collaborate to Provide Low Cost High Speed SerDes I/O Test .
Noise coupling is of major concern in the design of high wiring density packages with high speed SerDes (HSS) signals.