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Description: , such as the SerDes. The transimpedance amplifier is driven by a single +3.3 V power supply. The TGA4864 is manufactured in a reliable high-speed SiGe process that combines excellent performance together with cost-effectiveness.
- Supply Voltage (VS): 3.3 volts
- Supply Current (IS): 0.0750 amps
- Bandwidth: 3.60E10 Hz
- Package Type: Other
Standards and Technical Documents - ANSI INCITS 460 Standard Document -- INFORMATION TECHNOLOGY - FIBRE CHANNEL - PHYSICAL INTERFACE-3 (FC-PI-3)
Description: or technical report. This specification defines the electrical interfaces called XFI+ based on INF-8077(XFI) the XFP MSA for high-speed serial operation from 9.95-11.1 Gigabaud. This specification enhances the XFI specification to achieve greater printed circuit board (PCB) trace length and changes
Supplier: Howard Computers
Description: The TRP10GVP200x/210x is a highly integrated, serial optical transponder module for high-speed, 10Gbit/s data transmission applications. It is ideally suited for 10 GbE datacom (belly-to-belly for high density applications) and storage area network (SAN / NAS) applications based on the IEEE 802.3ae
- Network Equipment Type: Transceiver
- Protocols / Networks: Fibre Channel
- Data Rate: 1.05E7 kbps
Analog-to-Digital Converter (ADC) Chips - ISLA216S2516-Bit, 250MSPS JESD204B High Speed Serial Output ADC -- ISLA216S25Supplier: Techwell, Inc.
Description: Key Features JESD204A/B High Speed Data Interface JESD204A Compliant JESD204B Device Subclass 0 Compliant JESD204B Device Subclass 2 Compatible JESD204 Output Lanes Run up to 4.375Gbps Highly Configurable JESD204 Transmitter Multiple Chip Time Alignment and Deterministic Latency Support
- Resolution: 16 bits
- DNL: 0.2400 LSB
- INL: 16 LSB
- SNR: 75.8 dB
Supplier: ELMA Electronic Inc.
Description: to the next via high speed interconnecting cables, via signals introduced through the J1 fabric connector, or accessed on the J1 fabric connector using the test backplane’s SMA and SATA cable headers. For convenient testing of VPX boards Designed to the latest VITA 46.0 VPX specifications
- Board Function: Active Backplane
- Bus / Standard: Other
- Form Factor: 6U x 340mm (Size C)
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Integrated Device Technology
High-speed JESD204B Serial Interface DAC
IDT ’s DACs with JEDEC JESD204B-compliant interfaces are optimized for high-speed signal synthesis applications such as 3/4G wireless infrastructure equipment, high definition video broadcast and cutting edge instrumentation. They feature selectable interpolation ?lters, and up to eight JESD204B lanes serial interface with multiple device synchronization(MDS) capability. Key Features and Benefits: Dual and Quad channel DAC, 16-bit resolution. DAC update rate up to 2.0Gbps... (read more)
Browse Digital-to-Analog Converter (DAC) Chips Datasheets for Integrated Device Technology
Customize a fiber switch to almost any interface.
Use these Small Form-Factor Pluggable (SFP) Optical Transceivers to bring high-speed fiber and copper interfaces to any SFP slot. Because they come with different speeds, connectors, and types of media, they enable you to customize the SFP slot on your Ethernet switch to almost any interface, whether it ’s copper or fiber. Plus, they ’re hot-pluggable enabling you to change SFPs on the fly when your network requirements change. The SFPs are rated for extreme operating temperatures... (read more)
Browse Fiber Optic Transceivers Datasheets for Black Box
PinBuilder for XFdtd
signal integrity performance. Model generation with PinBuilder helps minimize return loss, insertion loss, and crosstalk within the pin-field of SerDes, memory busses, analog signal routing, and similar high-speed digital PCB designs. (read more)
Browse Datasheets for Remcom (USA)
Mentor Graphics Corporation
HyperLynx ® Signal Integrity (SI)
HyperLynx® Signal Integrity (SI) generates fast, easy and accurate signal integrity analysis in PCB systems design. HyperLynx SI helps engineers efficiently manage rule exploration, definition and validation, ensuring that engineering intent is fully achieved. The software is tightly integrated from schematic design through final layout verification. It can quickly and accurately resolve typical high-speed design effects including over/undershoot, ringing, crosstalk and timing. Comprehensive... (read more)
Browse Electronic Design Automation (EDA) and Electronic Computer-aided Design Software (ECAD) Datasheets for Mentor Graphics Corporation
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Estimating Clock Tree Jitter
system-level margin to reliably meet the application jitter requirements. If this jitter. threshold is exceeded in high-speed SerDes applications, for example, it could have a detrimental impact on the. Bit-Error Rate (BER) of the associated high-speed communications link. By ensuring jitter design
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High Speed Serdes Devices and Applications
The pin densities of chip packaging technologies have not increased at the same pace as has silicon density, and this has led to a prevalence of High Speed Serdes (HSS) devices as an inherent part of almost any chip design.
Low-Power Programmable Pseudorandom Word Generator and Clock Multiplier Unit for High-Speed SerDes Applications
In summary, a generic PFSR based, programmable PRWG ar- chitecture and a low noise, multiphase CMU are proposed for high speed SerDes applications.
Competitiveness and Technical Challenges of Low Cost Wirebond Packaging for High Speed SerDes Applications in ASICs
Competitiveness and Technical Challenges of Low Cost Wirebond Packaging for High Speed SerDes Applications in ASICs .
A 2.488–11.2 Gb/s SerDes in 40 nm low-leakage CMOS with multi-protocol compatibility for FPGA applications
His research interest include high speed Serdes , clocking and mixed-signal design.
An 8 × 8 20 Gbps Reconfigurable Load Balanced TDM Switch IC for High-Speed Networking
In this paper, we propose a load balanced Birkhoff-von Neumann symmetric TDM switch fabric architecture with high speed SERDES interfaces.
A 10th generation 16-core SPARC64 processor for mission-critical UNIX server
Figure 3.8.3: Block diagram of high speed SerDes with 8 TXs, 8 RXs and 2 PLLs feeding the physical coding sub-layer.
Dynamic arbitrary jitter injection method for ≫6.5Gb/s SerDes testing
However, the AWG must have a high enough sampling rate, several tens of GHz for high speed SerDes testing.
Survey of design and process failure modes for high-speed SerDes in nanometer CMOS
 G. Hetherington and R. Simpson, “Circular BIST testing the digital logic within a high speed Serdes ,�? Proc.
Cache Resident Functional Microprocessor Testing: Avoiding High Speed IO Issues
Microprocessor bus and mem ory interfaces have recently gone from some of the widest and fastest busses in the industry to the very newest tech nology, high speed SerDes links.
A 6.25 Gbps CMOS 10 B/8 B decoder with pipelined architecture
In the future, this decoder will be integrated into a high speed SerDes . . References .
Noise coupling is of major concern in the design of high wiring density packages with high speed SerDes (HSS) signals.
Design concepts for a hierarchical synchronized Data Acquisition network for CBM
Furthermore, the priority insertion of the deterministic latency messages (DLMs) allows to precisely time all endpoints and measure link latencies with resolutions of bit clocks of the high speed SERDES (200ps).
The role of optics in future high radix switch design
High speed SERDES can help by increas- ing the signaling rate, but this reduces the power budget available for the actual switching function.
Optimizing high speed serial communication using Honeywell Rad Hard SerDes
Communication networks that are developed with high speed SerDes embedded in an ASIC achieve significantly lower power, higher data throughput and more efficient area and weight usage than traditional parallel approaches for high-throughput backplanes and box-to-box network cabling systems.
Design and Implementation of Board-to-Board Optical Interconnect Protocol
For the tight requirements on clock of high speed SERDES , when the reference clocks of transmit port and receive port are not the same oscillator or have same frequency, the system has to do clock compensation.