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  • Estimating Clock Tree Jitter
    system-level margin to reliably meet the application jitter requirements. If this jitter. threshold is exceeded in high-speed SerDes applications, for example, it could have a detrimental impact on the. Bit-Error Rate (BER) of the associated high-speed communications link. By ensuring jitter design
  • MicroTCA TM: Compact, Flexible, Economical Shelf Architecture for Telecom Systems (.pdf)
    . and supports all of the protocol options defined for AdvancedMC. provides high-speed connectivity for the AdvancedMC modules,. modules, including Gigabit Ethernet, RapidIO, and PCI Express. giving up to eight protocol independent 12.5 Gb/s SERDES based. The MicroTCA backplane provides an I2C-based Integrated
  • 622 MBd ATM/SONET/SDH PHY Reference Design Development
    it is converted into high-speed. serial data and clock signals. In turn, the signals are converted to 8-bit parallel data by the. SerDes IC. The 8-bit data is then passed onto the framer IC and processed. The framer. output 16-bit bus is looped-back into the framer, this data is passed back

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