Spectrum Analyzers and Signal Analyzers - Signal Source Analyzer, 10 MHz to 7 GHz, 26.5 GHz, or 110 GHz -- Keysight Agilent HP E5052BSupplier: ValueTronics International, Inc.
Description: with the Keysight Agilent HP E5053A plus Keysight Agilent HP 11970 series mixers. The Keysight Agilent HP E5052B SSA is suitable for use in a wide range of applications including RF/uW/mmW oscillators, VCO's, system reference clocks, LAN modules, high-speed timing modules, SerDes chips, and high-speed data
Supplier: Integrated Device Technology
Description: has excellent phase jitter (< 1ps rms) suitable to clock components requiring precise and low-jitter sRIO clock signals. Designed for telecom, networking and industrial application, the 841664I can also drive the high-speed sRIO SerDes clock inputs of communication processors, DSPs, switches
- Device Type: Clock Generator
- Bus Interface / Output Type: Other
- Package / Form Factor: Surface Mount Technology (SMT), TSSOP
- Supply Voltage: 3.3 volts
Supplier: Intersil Corporation
Description: The ISL76322 is a serializer/deserializer of LVCMOS parallel video data. The video data presented to the serializer on the parallel LVCMOS bus is serialized into a high-speed differential signal. This differential signal is converted back to parallel video at the remote end by the deserializer
Supplier: Qorvo (TriQuint + RFMD)
Description: , such as the SerDes. The transimpedance amplifier is driven by a single +3.3 V power supply. The TGA4864 is manufactured in a reliable high-speed SiGe process that combines excellent performance together with cost-effectiveness.
- Supply Voltage (VS): 3.3 volts
- Supply Current (IS): 0.0750 amps
- Bandwidth: 3.60E10 Hz
- Package Type: Other
Analog-to-Digital Converter (ADC) Chips - 16-Bit, 130MSPS JESD204B High Speed Serial Output ADC -- ISLA216S13IR1ZSupplier: Intersil Corporation
Description: the ISLA216S from the ISLA216P is its highly configurable, JESD204B-compliant, high speed serial output link. The link offers data rates up to 4.375Gbps per lane and multiple packing modes. It uses two lanes to transmit the conversion data. The SERDES transmitter also provides deterministic latency
- IC Package Type: Other
- Resolution: 16 bits
- DNL: 0.1400 LSB
- INL: 9 LSB
Standards and Technical Documents - ANSI INCITS 460 Standard Document -- INFORMATION TECHNOLOGY - FIBRE CHANNEL - PHYSICAL INTERFACE-3 (FC-PI-3)
Description: or technical report. This specification defines the electrical interfaces called XFI+ based on INF-8077(XFI) the XFP MSA for high-speed serial operation from 9.95-11.1 Gigabaud. This specification enhances the XFI specification to achieve greater printed circuit board (PCB) trace length and changes
Analog-to-Digital Converter (ADC) Chips - ISLA216S2516-Bit, 250MSPS JESD204B High Speed Serial Output ADC -- ISLA216S25Supplier: Techwell, Inc.
Description: Key Features JESD204A/B High Speed Data Interface JESD204A Compliant JESD204B Device Subclass 0 Compliant JESD204B Device Subclass 2 Compatible JESD204 Output Lanes Run up to 4.375Gbps Highly Configurable JESD204 Transmitter Multiple Chip Time Alignment and Deterministic Latency Support
- Resolution: 16 bits
- DNL: 0.2400 LSB
- INL: 16 LSB
- SNR: 75.8 dB
Supplier: ELMA Electronic Inc.
Description: to the next via high speed interconnecting cables, via signals introduced through the J1 fabric connector, or accessed on the J1 fabric connector using the test backplane’s SMA and SATA cable headers. For convenient testing of VPX boards Designed to the latest VITA 46.0 VPX specifications
- Board Function: Active Backplane
- Bus / Standard: Other
- Form Factor: 6U x 340mm (Size C)
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High Speed Serdes Devices and Applications
The pin densities of chip packaging technologies have not increased at the same pace as has silicon density, and this has led to a prevalence of High Speed Serdes (HSS) devices as an inherent part of almost any chip design.
Low-Power Programmable Pseudorandom Word Generator and Clock Multiplier Unit for High-Speed SerDes Applications
In summary, a generic PFSR based, programmable PRWG ar- chitecture and a low noise, multiphase CMU are proposed for high speed SerDes applications.
A 2.488–11.2 Gb/s SerDes in 40 nm low-leakage CMOS with multi-protocol compatibility for FPGA applications
His research interest include high speed Serdes , clocking and mixed-signal design.
An 8 × 8 20 Gbps Reconfigurable Load Balanced TDM Switch IC for High-Speed Networking
In this paper, we propose a load balanced Birkhoff-von Neumann symmetric TDM switch fabric architecture with high speed SERDES interfaces.
A 10th generation 16-core SPARC64 processor for mission-critical UNIX server
Figure 3.8.3: Block diagram of high speed SerDes with 8 TXs, 8 RXs and 2 PLLs feeding the physical coding sub-layer.
Dynamic arbitrary jitter injection method for ≫6.5Gb/s SerDes testing
However, the AWG must have a high enough sampling rate, several tens of GHz for high speed SerDes testing.
Survey of design and process failure modes for high-speed SerDes in nanometer CMOS
 G. Hetherington and R. Simpson, “Circular BIST testing the digital logic within a high speed Serdes ,” Proc.
Cache Resident Functional Microprocessor Testing: Avoiding High Speed IO Issues
Microprocessor bus and mem ory interfaces have recently gone from some of the widest and fastest busses in the industry to the very newest tech nology, high speed SerDes links.
Noise coupling is of major concern in the design of high wiring density packages with high speed SerDes (HSS) signals.
A 6.25 Gbps CMOS 10 B/8 B decoder with pipelined architecture
In the future, this decoder will be integrated into a high speed SerDes . . References .
Design concepts for a hierarchical synchronized Data Acquisition network for CBM
Furthermore, the priority insertion of the deterministic latency messages (DLMs) allows to precisely time all endpoints and measure link latencies with resolutions of bit clocks of the high speed SERDES (200ps).
The role of optics in future high radix switch design
High speed SERDES can help by increas- ing the signaling rate, but this reduces the power budget available for the actual switching function.
Optimizing high speed serial communication using Honeywell Rad Hard SerDes
Communication networks that are developed with high speed SerDes embedded in an ASIC achieve significantly lower power, higher data throughput and more efficient area and weight usage than traditional parallel approaches for high-throughput backplanes and box-to-box network cabling systems.
Design and Implementation of Board-to-Board Optical Interconnect Protocol
For the tight requirements on clock of high speed SERDES , when the reference clocks of transmit port and receive port are not the same oscillator or have same frequency, the system has to do clock compensation.