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  • How much datalogging can an IPm Controller or RTU do?
    Just how much data can a SIXNET IPm-based DCS controller or RTU store? Use the steps below to calculate each datalog file size and the length of time you can store data in battery-backed memory or FLASH memory before the oldest data is overwritten. If multiple datalog files will be loaded into your
  • Freescale: Using HC08 Micro Controller Family to Enhance System Security
    Prevention of unauthorized reproduction of an embedded system intellectual property (IP) is achievable with the use of a device that provides on-chip IP protection capabilities. An example of such a device is a microcontroller unit (MCU) with embedded Flash memory featuring memory lock
  • EETimes.com | Electronics Industry News for EEs & Engineering Managers
    in new MP3 decoder ATI ups the ante for value PCs with 128-bit 3-D graphics chip set Cypress plans to double capacity at Minnesota fab, ramps advanced geometries ISSI issues 3.3 million shares of common stock Intersil aims to raise $500 million in IPO Xilinx releases memory controller design
  • Computer Power User Article - Advanced Q&A Corner
    , as inexpensive as it may be. That board is based on the VIA PT800 chipset and it doesn't support dual-channel DDR memory as you've suggested here. This will severely limit the system's overall memory bandwidth to virtually half that of a system with a dual-channel DDR-capable memory controller. Because you
  • Tomorrow's computers
    , graphic expansions, and disk storage. The basic C-brick module holds four Mips CPUs and local memory. A single crossbar memory controller delivers twice the CPU to memory bandwidth than pervious generations. The Raw (Raw architecture wiring) chip being developed at MIT's Laboratory of Computer
  • Computer Power User Article - SOYO SY-KT600 Dragon Ultra Platinum
    Sempron processors. The Dragon Ultra Platinum supports FSB speeds up to 400MHz. The FastStream64 single-channel memory controller doesn't support dual-channel configurations, unfortunately. An 8X V-Link bus connects the northbridge to the southbridge for up to 533MBps of throughput. The VT8237
  • Computer Power User Article - Building The Ultimate PC
    and independent 1MB L2 caches. These interface with a request queue and crossbar, enabling communication between them at full processor speed. The only downside is that both cores must share one integrated memory controller and the HyperTransport link. Fortunately, there s plenty of bandwidth
  • Computer Power User Article - Components We Crave
    and performance. AMD moved to its Socket AM2 platform and surgically replaced the K8 s DDR memory controller with one that supported faster DDR2 RAM, but the switch to a different memory type wasn t enough to keep pace with Intel s new baby. With that, we declare Intel s Core 2 Extreme X6800 and QX6700