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Conduct Research Top

  • Programmable Controllers
    that permits a user to tie into a computer. Three developments have helped bring about this integration of PLCs and computers: "smart " PLCs with their own microprocessors and memory, multitasking software, and local-area networks (LANs). New software has enhanced the capability of computers
  • How much datalogging can an IPm Controller or RTU do?
    Just how much data can a SIXNET IPm-based DCS controller or RTU store? Use the steps below to calculate each datalog file size and the length of time you can store data in battery-backed memory or FLASH memory before the oldest data is overwritten. If multiple datalog files will be loaded into your
  • Monitoring Automotive Engine Controllers
    channel of acquisition memory.
  • Freescale: Using HC08 Micro Controller Family to Enhance System Security
    Prevention of unauthorized reproduction of an embedded system intellectual property (IP) is achievable with the use of a device that provides on-chip IP protection capabilities. An example of such a device is a microcontroller unit (MCU) with embedded Flash memory featuring memory lock
  • Computer Power User Article - DFI NFII Ultra Infinity
    memory controllers for high-speed, low-latency memory bandwidth between matched modules. The Silicon Image SATALink controller handles the Serial ATA ports that provide 150MBps throughput for up to four devices. DFI decided to go with the Ultra 400R version of NVIDIA's MCP-T (Media and Communications
  • | Electronics Industry News for EEs & Engineering Managers
    in new MP3 decoder ATI ups the ante for value PCs with 128-bit 3-D graphics chip set Cypress plans to double capacity at Minnesota fab, ramps advanced geometries ISSI issues 3.3 million shares of common stock Intersil aims to raise $500 million in IPO Xilinx releases memory controller design
  • Computer Power User Article - Advanced Q&A Corner
    , as inexpensive as it may be. That board is based on the VIA PT800 chipset and it doesn't support dual-channel DDR memory as you've suggested here. This will severely limit the system's overall memory bandwidth to virtually half that of a system with a dual-channel DDR-capable memory controller. Because you
  • Tomorrow's computers
    , graphic expansions, and disk storage. The basic C-brick module holds four Mips CPUs and local memory. A single crossbar memory controller delivers twice the CPU to memory bandwidth than pervious generations. The Raw (Raw architecture wiring) chip being developed at MIT's Laboratory of Computer