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  • The Future of PCIe in the Industrial Sector
    the standard UART found on PCI boards. Therefore, they require an additional PCIe interface bridge chip to transform the board into a full-fledged PCI Express board. Earlier this year, a new native solution was introduced that eliminates the need for two separate chips on PCIe serial boards. The new
  • PCIe? USB? Sorting Out Two COM / SFF Design Decisions
    the same low latency. PCIe, then, is both less latent and higher-bandwidth than USB even can be. So why should you even consider USB?. USB is easy and inexpensive to design. USB Bus interface chips are simple, relatively low pin-count devices, allowing fewer layers to be used in the design. USB 1.1
  • Features of the StackableUSB TM Interface: A New Specification for I/O Expansion in Embedded PCs
    interface. desktop PC using a cable and. chips make design easy,. and many of the chips. An abundance of. include some of the. more common control. USB interface. functions that users of. chips make design. embedded systems. need. easy, and many of. StackableUSB 2.0 has. the chips include. faster throughput
  • PCI Express (R): Selecting the Right Bridge for High Performance Applications
    interconnect support for both chip-to-chip and add-in card applications. PCIe offers many advantages over conventional PCI and PCI/X: It offers higher speed, is scalable from 1 to 32 lanes of 2.5Gbps for a single 80Gbps link, compared to maximum 8Gbps for 64-bit PCI/X at 133 MHz. Additionally as a serial
  • Advanced Switching Interconnect (ASI) Sets New Benchmarks in Networking Over the Backplane (.pdf)
    be used like. cost-effectiveness. The PCI Express (PCIe)-based. PCIe. expansion technology Advanced Switching. Interconnect (ASI) combines exactly these. advantages, and thus has all that it takes to. position itself, in this respect, as a future-. oriented alternative, alongside Gigabit Ethernet
  • Point Grey USB 3.0 FAQ & Practical Guide to Machine Vision
    chipset and the motherboard. chipset. For example, some Intel motherboards limit the PCIe Gen 2.0 x1 interface to Gen 1.0 speeds (2.5 Gb/s instead of 5Gb/s). Click. here for a summary of Point Grey recommended hardware configurations. In 2013, the USB 3.0 Promoter Group announced plans to. enhance
  • PCI Express Peer-to-Peer Interconnect (.pdf)
    implementations are vendor-specific, with. upstream host controller. each vendor defining a unique interface mechanism for configu-. ration and signaling in which the end goal is always the same - to. Within the PCIe domain, peripherals are termed endpoint devices: bridge PCIe domains. these endpoint devices
  • Computer Power User Article - Advanced Q&A Corner
    by a custom chip Nvidia designed for use on the GeForce 7950 GX2. The GX2 also has a PCI Express switch that lets each GPU communicate with the system via a single PCI-E x16 link. The two GPUs on the 7950 GX2 can interface through the switch peer-to-peer, as well. According to Nvidia, the reason
  • Computer Power User Article - What's Happening
    lets chip jockeys push their FSB to 2.28GHz and memory to 1.3GHz. An Extreme Tweaker interface gives DIYers one-stop access to the most important overclocking tools, while an LCD reports inevitable error messages. Because most of us build systems outside of the case, Asus also includes a single
  • PCI Express Advances Machine Vision
    , that simplify the addition. driver, operating system, and application levels. The hardware for a. of new functions if the operating system supports them. PCIe link handles the transition from parallel, memory-mapped data. Peripherals with a native PCIe interface are also positioned to. transfers of PCI