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Phase-locked Loops (PLLs)

 

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Part # Distributor Manufacturer Product Category Description
MC74HC4046AF Digi-Key ON Semiconductor Integrated Circuits (ICs) IC PHASE LOCKED LOOP 16-SOEIAJ
MC14046BDWG Digi-Key ON Semiconductor Integrated Circuits (ICs) IC PHASE LOCKED LOOP 16-SOIC
MC14046BFELG Digi-Key ON Semiconductor Integrated Circuits (ICs) IC PHASE LOCKED LOOP 16SOEIAJ
TLC2933IPWR Digi-Key Texas Instruments Integrated Circuits (ICs) IC PHASE-LOCKED LOOP 14-TSSOP
CD74ACT297M96 Digi-Key Texas Instruments Integrated Circuits (ICs) IC DGTL PHASE-LOCKED LOOP 16SOIC
LMC568CMX/NOPB Digi-Key Texas Instruments Integrated Circuits (ICs) IC PHASE-LOCKED LOOP LOPWR 8SOIC
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  • A PRIMER ON JITTER, JITTER MEASUREMENT AND PHASE-LOCKED LOOPS
    assistance in making jitter measurements, and. examines the role phase-locked loops (PLLs) have in this field.
  • Phase-Locked Loops for Wireless Communications: Digital, Analog and Optical Implementations, Second Edition
    Phase-Locked Loops for Wireless Communications: Digital, Analog and Optical Implementations, Second Edition. Starting with a historical overview, presenting analog, digital, and optical PLLs, discussing phase noise analysis, and including circuits/algorithms for data synchronization, this volume
  • Basics of Dual Fractional-N Synthesizers/PLLs
    . A frequency divider is,. basically, a state machine clocked by the VCO. A rising edge occurs at the divider output every N number of VCO. Basics of Phase Locked Loops (PLLs). cycles. Here, N is a predetermined number and is referred to as. A PLL is a negative feedback loop in which the phase
  • PLL Jitter and its Effects on ECANTM Technology Communications (.pdf)
    programmable PLLs in their clock generation circuits. One point of interest in the use of PLL circuits is that they create a small, but still measurable, level of transient phase shifts, or jitter. This technical brief shows the influence of PLL jitter on CAN communications using the dsPIC33F/PIC24H
  • PLL Jitter and Its Effects in the CAN Protocol
    Phase Locked Loop (PLL) circuits are increasingly used in microcontrollers to achieve higher internal clock frequencies. This allows better performance while reducing overall noise. Several of Microchip's PIC18 microcontrollers feature 4x PLLs in their clock generation circuits. This makes
  • Power Supply Rejection for Low Jitter Clocks
    performance when subjected to power supply ripple. Timing devices often rely on phase-locked loops (PLLs) to perform various functions, such as jitter filtering and. frequency multiplication. One of the primary challenges in PLL design is associated with its voltage-controlled. oscillator (VCO). To meet
  • Interfacing a KEELOQ(R) Encoder to a PLL Circuit
    unit (TE). Refer to the HCS362 data sheet. ing a reasonable efficiency and operating range. [DS40189] Power-up and Transmit Timing Figure 8-1,. Table 8-3, and parameter TRFON. INTERFACING TO PLLS. RFEN output can be used as an ASK enable signal by. The objective of this Technical Brief
  • Phase Coherent Multi-Channel RF Synthesis (.pdf)
    to an L-C or R-C filter response. When. applying a step response, these basic circuits will settle to near the final value. very fast, but then takes an order of magnitude greater time to settle to a very. exact value. Even fast tuning PLLs will take 10us-100us to settle to a precise. value. Phase

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