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  • Low-Power VLSI Circuits and Systems
    � logic � Double pass-transistor logic � Charge sharing problem � Charge leakage problem � Clock skew � Domino CMOS � NORA CMOS � Fan-in � Fan-out � Switching characteristic � Pre-charge logic � Priority encoder � Parity generator On the other hand, gate logic is based on the realization of digital circuits using inverters and other conventional gates, as it is typically done in transistor � transistor logic (TTL) circuits.
  • Abstracts of Current Computer Literature
    � Level NAND Networks of General Boolean Functions 8142 Use of a Tri-Stable Diode-Transistor Circuit in a Ternary Feedback Shift Register 8154 Tests Generation of Tests in Logic Design 7295 Heuristic Methods � � System 4 Random Number Generator 7581 Testing the Linearity � � Arbitrary Switching Func- tion with a Two-Level Network of Thresh- old and Parity Modules 7905 Synthesis � � Systems 8173 -see also Multiple-Access, Multiprogram- ming, Remote, Teleprocessing Training Electrochemically Active Field-Trainable Pattern Recognition Systems 7415 Useful Form of Potential Function for Lin- early Separable Training Patterns 7711 -see also Adaptive, Education, Learning Transistors ; Transistor Circuits Switching and Storage �
  • Abstracts of Current Computer Literature
    � of a 64-Output MOS Tran- sistor Selection Tree for Display and Storage 6533 MOS Field-Effect Transistor Drivers for Laminated-Ferrite Memories 6534 Design of Subnanosecond Current Switch and Transistors for Integrated Circuits 6685 Transistor - Transistor Logic with High Packing Density � � Utilization of Faulty Uni- versal Cellular Tree Circuits 6967 Machine that Identifies the Parity of the Number � � Technique for Plated Wire Memories 6543 Word-Organized Storage Arrays 6615 Pushbutton Word Generators for Remote Computer �
  • A 0.6-W 10-Gb/s SONET/SDH bit-error-rate monitoring LSI
    Measurements were performed on the wafer using an RF probe card and a 10-Gb/s pattern generator . The following eight bits in the B1 error are the difference between the parity calculated in the � Supply voltage is 3.3 V, except for transistor - transistor logic (TTL) I/O ( 3.3 V).
  • Practical electronics
    Parallel circuit, 7 parity checks, 229, 231 level converters, 94, 111 level transducers, 111 permeability, 116 phase � � 291-294 CAN 294 RS232, 293 professional bus, RS422 291 SSI, RS485, 295 USB, 293 interface-circuits, 108, 215 step chain, 236 protection circuit 157 Separierbarkeit, 194 threshold logic , 158 set dominantly 41 � � 176 Signumschalter, 90 sine generator , 92 skin equations 117 � Order, 63 dead times, 248 transistors 109, 81 separating amplifiers, TTL switching circuits, 219 .
  • Electrical measurement
    � 149 linearity errors 267, 279, 337, 363 line spectrum 449 14 light pointers to Lenzsche rule 121 ? illuminating layer 264 speed of light 13 light intensity 11, 12 luminous flux with diode 188 with transistor 189 logic negative 297, 537 positive � � 500 module-library 649 O?ine 499 Online, 499 Power line-communication 620 program generator 649 Quittierung method � bit 522 PCI-express 508, 516, 552, 555, 559, 653 period duration measurement 402, 421, 422 relative �
  • Digital circuit applications of resonant tunneling devices
    Each circuit contained just one or two quantum devices; a three-state memory cell consisted of two RTD�s and a couple of resistors, a parity generator consisted of just one RTT, and so on. A full adder that requires 45 transistors and several resistors in a conventional bipolar technology, such as transistor � transistor logic requires only seven RHET�s and a few resistors.
  • Elements of the applied electronics
    � voltage negative feedback 146,160-converter 272, 273, parasitic 116, 118, 212, 292 parity testers 414 PC � � FET 108, 109, 394 P core 63 planar / - diode 356, 376, epitaxial transistor 356, process 356 � � Rail 166, 401 RAM 266, 267, 416 - - system 435 - - cell 435 ramp / generator 233, 318, voltage � � 202, 400 noise 192, voltage 58, 93 circuit, printed 302, 356 integrated 124, logical 236, 238 et �
  • Microcomputer technique
    Message � 101, 102 negative logic � 94 Nibble mode � 123 NMI (Non-maskable interrupt) � � Parity � 128 Parit�tsbit � 127, 129, 132 Parity error � 265 pause signal � 127, 129 � � string � 103 Pseudo - LRU method � 62-tetrad � 163-random number- generator � 68 pulse � Schalt - speed � 140- transistor � 105 schedulers � 74 Push the - normalizing-unit � 89 - the �
  • Abstracts of Current Computer Literature
    � old Switching Theory 8842 Time-Sharing Analysis of Some Time-Sharing Techniques 8820 A Policy-Driven Scheduler for a Time-Shar- ing Operating System 8821 Transistors; Transistor Circuits Transistor Array High-Speed READ � � Testability of Combina- tional Logic Tree Networks 8780 Probability � � 8861 Characteristic Functions 8857 Chebyshev-Fourier Coefficient 8844 Class Set 8788 Clock Pulse Generator 8790 Clustering 8856 � Overlay 8820 p Padel Language 8824, 8825 Paramodulation 8832 Parity Check 8792 PDP-7 Application 8827 Perfect �
  • Single-chip 4�500-MBd CMOS transceiver
    � ex- ternal delay variations affecting the output interface, a dedi- cated PLL clock generator (Fig. 9, bottom � A parity bit is generated for all but the last byte of an LU and is delivered � All standard-cell logic circuits follow level-sensitive scan design rules. All transistor - transistor logic- (TTL-) level off-chip receivers and drivers are connected directly to latch inputs and outputs, respectively,to satisfy boundary scan rules.
  • A Novel Parallel Binary Counter Design with Parity Prediction and Error Detection Scheme
    The 27-gate binary counter (Fig. 9) and the 19-gate error detection circuit (Fig. 8), not including the parity generator circuit, contain 207 possible faults, 124 in the counter and 83 in error detection circuitry. This reduces the number of logic gates and gives a more efficient design. [5] B. T. Murophy and V. J. Clinski, " Transistor - transistor logic with high packing density and optimum performance at high inverse gain," 1968 Int.