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  • Reducing defect density using an optimized wafer scrubber
    Beverly Albrecht, Lisa Fritz, and Randy Solis, To ensure high device yields, wafer surface contamination and defects must be monitored and controlled at several points in the semiconductor manufacturing process. Wafer scrubbers are among the tools used to achieve such control. This article
  • MICRO:Defect Inspection Equipment, by Thomas Reuter (Oct '99)
    -of- line (BEOL) metal etch steps, defects are generated that can disable devices and lead to yield losses. To meet the challenge of defect detection and reduction on ever-smaller devices, the AIT II, a next- generation patterned-wafer inspection tool from KLA-Tencor (San Jose), was installed at Infineon
  • MICRO: Best of ASMC- Williams (January 2001)
    Randy Williams and Robert Jacques, ; and Mustafa Akbulut and Wayne Chen, A collaborative study that used an advanced unpatterned wafer inspection system found that epitaxial defects and their corresponding impact on device yield varied between wafer suppliers. Silicon wafers with an epitaxially
    of the company's wafer inspection division. Applied Materials paid approximately $285 million to buy two Israel-based
  • MICRO:Analysis and Metrology-Yield Management, by David Guidry (Oct '99)
    in-line defect inspection data with end-of-line bitmap failure data for analysis. Such advanced software has greatly increased the ability of engineers to analyze bitmap data. Whereas in the past failure analysis involved painstaking visual wafer inspections, interspersed with difficult deprocessing
  • MICRO: E A & A
    KLA-Tencor and Soitec have joined forces to develop the first wafer-inspection system optimized for silicon-on-insulator (SOI) applications in the 90- and 65-nm nodes. The tool will be based on KLA-T's Surfscan SP1 platform, with the initial system shipping to Soitec's Bernin, France, site in early
  • MICRO: Defect Metrology
    required to optimize the process step. Compared with manual defect review, real-time automated defect classification may also increase the wafer-inspection sampling rate, reduce the amount of work in process at risk, and reduce cycle times. To assess its capabilities, an automated wafer inspection
  • MICRO:Analysis & Metrology by Reinhold Ott p.48 (June '99)
    , effective yield management requires both reliable defect information and rapid defect-source identification. Traditionally, defect reduction and yield enhancement strategies have followed a set sequence of events. Defects are captured and located with a wafer inspection system. Then a small subset
  • | Electronics Industry News for EEs & Engineering Managers
    software with IA-64 patents NEW YORK -- A flurry of more than 20 new patents suggests Intel Corp. is expanding its time-tested legal strategy to prevent cloning of its new, flagship IA-64 architecture. ADE claims KLA-Tencor violating wafer inspection patent WESTWOOD, Mass. -- ADE Corp. here has

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