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  • Metal Based Wafer Bonding Techniques for Wafer Level Packaging (.pdf)
    Wafer level bonding utilizing metal based technologies are coming to the forefront of manufacturing methods in numerous 3D integration schemes and advanced MEMS processing. Copper to copper bonding of TSVs (through silicon vias) is used for 3D IC stacking of individual layers as well as in 3D
  • Screen Printable Polymers for Wafer Level Packaging: A Technology Assessment (.pdf)
    as masked off saw streets and I/Os across the wafer. Thickness comparisons are made between the 2 methodologies.
  • | Electronics Industry News for EEs & Engineering Managers
    Consortium develops first wafer-level packaging technologies for 300-mm wafers SANTA CLARA, Calif. -- A consortium has demonstrated what is believed to be the world's first wafer-level packaging technologies for 300-mm silicon substrates. The consortium, called the Semiconductor Equipment
  • | Electronics Industry News for EEs & Engineering Managers
    Despite plane crash Appleton plans to speak at Semicon Structured ASIC market to grow 55%, says Semico FlipChip to expand wafer-level packaging capacity Cimetrix rolls out beta program for Interface A software Broadband to continue rapid worldwide growth Broadband-subscriber growth on a worldwide
  • | Electronics Industry News for EEs & Engineering Managers
    . Amkor provides glimpse of future chip-packages Japan's Selete takes delivery of first EPL tool Wafer-level packaging group sets up 300-mm line Amkor provides glimpse of future IC-packages Providing a glimpse into the future of IC-packaging, Amkor Technology Inc. outlined its roadmap, disclosing plans
  • Semiconductor and IC Package Testing
    Semiconductor, microelectronic, and IC package testing includes testing at the wafer, die, or packaged IC level. Semiconductor and IC package testing services may provide wafer sort and packaging services in addition to component evaluation. In the packaging process, fabricated wafers are cut
  • MICRO:Shive (March 2001)
    Larry W. Shive, Richard E. Blank, and Karen H. Lamb, Study results indicate that time-dependent haze can be caused by humidity inside wafer packaging and by organic or ionic contamination on the wafer surface that exceeds typical levels. Silicon wafer users expect that the surface of the wafers
  • | Electronics Industry News for EEs & Engineering Managers
    Amkor goes wafer-bumping with Unitive Amkor Technology Inc.'s move this week to acquire a wafer-bump company will enable the IC-packaging giant to expand its wings in the flip-chip, wafer-level and related markets, according to an executive with the company. DoD spending bill includes

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