Static random access memory (SRAM) chips are dual-transistor memory cells that require a constant supply of power in order to retain their content. Each SRAM bit is a flip-flop circuit made of cross-coupled inverters. The activation of transistors controls the flow of current from one side to the other. The transistors are connected so that one only transistor is in or out at any time. When power is received, all SRAM cells are in a logical state of 1 (ON). Subsequent data writing changes some of the cells to a logical stage of 0 (OFF). This state is maintained until the next write operation, or when power is removed. Because they use multiple transistors, SRAM memory chips are more expensive and require more power than DRAM memory chips; however, because they do not need to be constantly refreshed, SRAM memory chips are faster and more reliable. Common applications for SRAM memory chips include system caches and video memory.
Important specifications for SRAM memory chips include density, number of words, bits per word, access time, cycle time, data rate, supply voltage, data retention voltage, and data retention current. Density is the capacity of the chip in bits. The number of words equals the number of rows, each of which stores a memory word and connects to a word line for addressing purposes. The bits per word are the number of columns, each of which connects to a sense/write circuit. Supply voltages range from - 5 V to 5 V and include many intermediate voltages. Measured in nanoseconds (ns), access time indicates the speed of memory and represents a cycle that begins when the central processing unit (CPU) sends a request to memory and ends when the CPU receives the data requested. Cycle time is the time required to both perform a single read or write operation and reset the internal circuitry so another operation can begin. Data retention voltage and data retention current are, respectively, the minimum voltage and minimum current that SRAM memory cells must maintain in order to preserve stored data. Measured in hertz (Hz), data rate is the number of bits per second that can be moved internally.
Selecting SRAM Memory Chips
Selecting SRAM memory chips requires an analysis of logic families. Transistor-transistor logic (TTL) and related technologies such as Fairchild advanced Schottky TTL (FAST) use transistors as digital switches. By contrast, emitter coupled logic (ECL) uses transistors to steer current through gates that compute logical functions. Another logic family, complementary metal-oxide semiconductor (CMOS) uses a combination of p-type and n-type metal-oxide-semiconductor field effect transistors (MOSFET) to implement logic gates and other digital circuits. Logic families for SRAM memory chips include cross-bar switch technology (CBT), gallium arsenide (GaAs), integrated injection logic (I2L) and silicon on sapphire (SOS). Gunning with transceiver logic (GTL) and gunning with transceiver logic plus (GTLP) are also available.
IC Package Types
SRAM memory chips are available in a variety of IC package types and with different numbers of pins. Basic IC package types for SRAM memory chips include ball grid array (BGA), quad flat package (QFP), single in-line package (SIP), and dual in-line package (DIP). Many packaging variants are available. For example, BGA variants include plastic-ball grid array (PBGA) and tape-ball grid array (TBGA). QFP variants include low-profile quad flat package (LQFP) and thin quad flat package (TQFP). DIPs are available in either ceramic (CDIP) or plastic (PDIP). Other IC package types include small outline package (SOP), thin small outline package (TSOP), and shrink small outline package (SSOP).
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