Editor’s note: This special print issue of www.DSP-FPGA.com comes out only once a year, so we have to cover 12 months’ worth of technology in only 700 words. Check out the website and E-letter for monthly trends.
A year ago I expressed surprise that FPGAs still weren’t in cell phones and that coding signal processing algorithms such as video remained difficult. What a difference a year makes. Although FPGA architects still need skills as IC designers, that mythical “C to silicon” tool doesn’t yet exist, but it’s closer.
Mentor Graphics’ Precision RTL Plus
The fact that Mentor’s innovative new product still says “RTL” in the title means FPGA designers can’t completely ignore the silicon architecture or the vendor’s synthesis tools. The product promises three key improvements: 1) silicon-aware synthesis, 2) automatic incremental synthesis, and 3) vastly improved design optimization. If you’ve got to dig into the silicon in the first place, you might as well wring everything possible from it.
With physically aware synthesis, the tool takes advantage of vendor design rules in 19 families from Actel, Altera, Lattice, and Xilinx. Mentor’s own tests reveal a 5-40 percent increase in device clock speed, with an “average Fmax improvement of 10 percent.” Xilinx’s tests on a Virtex-5 (latest gen) with a V2 ColdFire 32-bit CPU core showed a 17 percent increase to 95 MHz. The significance here is not only faster system throughput, but also the ability to buy a lower-speed grade device, saving recurring silicon costs. Also, fewer place and route iterations are needed to achieve target performance, saving tons of expensive designer cycles as well as time to market.