In this application note, the following definitions apply: Cycle-to-cycle jitter-The short-term variation in clock period between adjacent clock cycles. This jitter measure, abbreviated here as JCC,...
3.2.3 Timing Aspects
In modern networks, the bit rate has exceeded by far the gigabit per second rate and,
therefore, the performance of timing circuitry must meet stringent specifications.
High speed, high performance timing applications often require a combination of XO/VCXOs, clock generators,
clock buffers and jitter cleaning clocks to satisfy system timing requirements. Each...
3.3 Jitter in PLLs
The main concern for jitter in digital systems is the decrease in timing margin that it causes. Controlling jitter allows more flexibility in the timing budget.
Refers to user adoption of Serial ATA, where Serial ATA is often seen in homes and businesses.
Acronym for cyclic redundancy check. Used to verify the...