Copper/low-k dielectric interconnect has legs, but for how long? The replacement of aluminum with copper and the advent of low-k dielectric insulators in logic back-end-of-line interconnect schemes has been one of the most successful materials integration change-overs in chipmaking history. Although it appears the damascene tandem will continue to push down the scaling roadmap for awhile, alternative interconnect options will be needed in the not-too-distant future. This issue’s Hot Button participants weigh in on the background, current and near-term outlook, and longer-term challenges of BEOL processing. STEPHEN LUCE (distinguished engineer, IBM Microelectronics): Chip performance continues to improve with each technology generation. This steady progress is driven by predictable improvements in transistors and ongoing enhancements in chip architecture. Delay from chip interconnects was not a serious limiter to ever-increasing chip speeds for the first three decades of IC manufacturing, so the interconnect material set of aluminum conductors and silicon dioxide insulators remained unchanged. But in the mid-to-late 1990s, chip speeds had increased to
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Chemical mechanical planarization (CMP) slurries consist of surface active chemicals and microabrasive  grains in a liquid dispersion.

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Topics of Interest

Surface prep, cleaning, stripping of low-k dielectrics, copper interconnects become more problematic Whether it's in the front end or the back end of the process line, the cleaning, stripping, and...

Dow Corning has been granted a patent in Japan covering the use of silicon carbide barrier films between dielectric and metal layers. Silicon carbide barrier technology is essential in the production...

Copper electroplating, CMP challenges grow more complex at 65-nm node and beyond The back-end-of-line (BEOL) challenges facing fab teams as they develop and ramp the 65-, 45-, and 32-nm nodes will...

and Gaurav Virendra Gupta, A spin-process technique prevents back-surface particle contamination of the process chuck, creates an edge exclusion zone, and optimizes the copper/barrier material...

Materials, Cost, Productivity, and Risk Management Top the List is chief technology officer and senior vice president, semiconductor technology research, for The Noblemen Group, a boutique investment...