Chapter 15: Debug Architecture

Debugging Features Overview

The Cortex-M3 processor provides a comprehensive debugging environment. Based on the nature of operations, the debugging features can be classified into two groups:

1. Invasive debugging:

   • Program halt and stepping

   • Hardware breakpoints

   • Breakpoint instruction

   • Data watchpoint on access to data address, address range, or data value

   • Register value accesses (both read or write)

   • Debug monitor exception

   • ROM-based debugging (Flash patch)

2. Noninvasive debugging:

   • Memory accesses (memory contents can be accessed even when the core is running)

   • Instruction trace (via the optional Embedded Trace Module)

   • Data trace

   • Software trace (via the Instrumentation Trace Module)

   • Profiling (via the Data Watchpoint and Trace Module)

A number of debugging components are included in the Cortex-M3 processor. The debugging system is based on the CoreSight debug architecture, allowing a standardized solution to access debugging controls, gather trace information, and detect debugging system configuration.

CoreSight Overview

The CoreSight debug architecture covers a wide area, including the debugging interface protocol, debugging bus protocol, control of debugging components, security features, trace data interface, and more. The CoreSight Technology System Design Guide (Ref 3) is a useful document for getting an overview of the architecture. In addition, a number of sections in the Cortex-M3 Technical Reference Manual (Ref 1) are descriptions of the debugging components in Cortex-M3 design. These components are normally used only by debugger software, not by application code. However, it is still useful to briefly review these items so that we can have a better understanding of how the debugging system works.