3.3 Jitter in PLLs
The main concern for jitter in digital systems is the decrease in timing margin that it causes. Controlling jitter allows more flexibility in the timing budget.
For example,...
In this application note, the following definitions apply: Cycle-to-cycle jitter-The short-term variation in clock period between adjacent clock cycles. This jitter measure, abbreviated here as JCC,...
High speed, high performance timing applications often require a combination of XO/VCXOs, clock generators,
clock buffers and jitter cleaning clocks to satisfy system timing requirements. Each...
With increasing transfer rates and lower jitter margins, the performance of clock generation circuits has become of increasing importance. A key measurement of the performance of clock circuits is...
Phase Locked Loop (PLL) circuits are increasingly used in microcontrollers to achieve higher internal clock frequencies. Incorporation of PLL circuits allows better performance while reducing overall...
