From Skyworks Solutions, Inc.
Low cost processes, in both GaAs and Silicon, often
use non-planar interconnect metals. While very efficient in
simplifying processes, seam (more commonly called "crack")
formation due to inter-level dielectric topologies can (1) cause
significant thinning in the metallization, impacting the reliability
and (2) act as process defect that reduces circuit yield. To better
understand and monitor crack formation, we used a series of test
structures to develop an electrical test allowing crack formation
to be characterized. We confirmed our results with cross
sections. The methodology developed here is also used during the
development of new process steps/processes to make sure the new
process does not result in worse cracking and led to the
identification of a design rule need in a process we were
developing.
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Topics of Interest
Abhay Ramrao Deshmukh, National Semiconductor he planarization of interlevel dielectric (ILD) is critical to the success of multilevel metallization processes. In multilevel metallization, patterned...
and Steve Ellinger and Daniel Morvay, In a new defect reduction strategy, patterned wafers replace bare silicon wafers to perform line monitoring and detect particles responsible for yield loss on...
Multiple factors need to be considered when selecting an interlevel dielectric material for GaAs semiconductor device fabrication including what the electrical, mechanical, chemical, thermal, and cost...
Jeffery W. Butterbaugh, Steve Loper, and Greg Thomes, As the number of metallization levels in IC manufacturing increases, it becomes more critical to control and reduce defects at each step of the...
5.1 Introduction Analytical methods based on the work done by applied loads and the changes in the energy of a system that accompany a real or virtual crack advance have been of central importance...
