From The System Designer's Guide to VHDL-AMS: Analog, Mixed-Signal, and Mixed-Technology Modeling

The concepts of type and nature are very important when describing data in a VHDL-AMS model. The type or nature of a data object defines the set of values that the object can assume, as well as the set of operations that can be performed on those values. A scalar type consists of single, indivisible values. A scalar nature defines values that are associated with a single terminal. In this chapter we look at the basic scalar types and natures provided by VHDL-AMS and see how they can be used to define data objects that model the internal state of a module.

2.1 Constants and Variables

An object is a named item in a VHDL-AMS model that has a value of a specified type or, in the case of a terminal, has a specified nature. There are six classes of objects: constants, variables, signals, terminals, quantities and files. In this chapter, we look at constants and variables; signals are described fully in Chapter 5, terminals and quantities in Chapter 6, and files in Chapter 21. Constants and variables are objects in which data can be stored for use in a model. The difference between them is that the value of a constant cannot be changed after it is created, whereas a variable's value can be changed as many times as necessary using variable assignment statements.

Constant and Variable Declarations

Both constants and variables need to be declared before they can be used in a model. A declaration simply introduces...

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Topics of Interest

In the previous chapter we saw how to represent the internal state of models using VHDL-AMS data types and natures. In this chapter we look at how that data may be manipulated within processes and...

The concept of type is very important when describing data in a VHDL model. The type of a data object defines the set of values that the object can assume, as well as the set of operations that can be...

Now that we have seen the basic data types, natures and sequential operations from which the processes of a VHDL-AMS model are formed, it is time to look at composite data types. We first mentioned...

We have seen in previous chapters how we can use variables within processes to create data that is associated with a name. We can write a variable name in a model to read its value in expressions and...

A model of an analog system consists of the circuit nodes, analog unknowns to be calculated and the characteristic equations that specify analog behavior. In VHDL-AMS, we use terminals to represent...