5.4: Boundary scan and IEEE standard 1149.1

5.4 Boundary scan and IEEE standard 1149.1

Boundary scan is primarily concerned with delivering test signals to and collecting response signals from the I/Os of several integrated circuits which have been assembled into a complete working system, rather than the testing of an individual unconnected IC. It is therefore a board-level testing tool for the use of the OEM, enabling faulty items and interconnections to be detected and hopefully replaced or repaired.

The development of boundary scan originated with OEM designers in Europe who were involved with the design of very complex printed circuit boards (PCBs) and their test after assembly, and where decreasing spacing between conductors and components was making test probing more difficult (see Chapter 1, Section 1.5). As a result the Joint European Test Action Group (JETAG) was established in 1985, which subsequently grew into the Joint Test Action Group (JTAG) when North American companies later joined. Their work resulted in the IEEE Standard 1149.1-1990, entitled 'standard test access port and boundary scan architecture' ^{[42] [43] [44]}. The IEEE 1149 working group now maintains and updates this standard, which has been accepted internationally by all IC manufacturers. In all that follows the circuits, test procedures and terminology will be based upon standard 1149.

The essence of boundary scan is to include a boundary scan cell in every I/O circuit, as shown in Figure 5.18. During normal-mode working, system data passes freely through all the boundary cells from NDI to NDO, but in test mode...