 | This text/reference provides students and practicing engineers with an introduction to the classical methods of designing electrical circuits, but incorporates modern logic design techniques used in the latest microprocessors, microcontrollers, microcomputers, and various LSI components. The book provides a review of the classical methods e.g., the basic concepts of Boolean algebra, combinational logic and sequential logic procedures, before engaging in the practical design approach and the use of computer-aided tools. The book is enriched with numerous examples (and their solutions), over 500 illustrations, and includes a CD-ROM with simulations, additional figures, and third party software to illustrate the concepts discussed in the book. |
TABLE OF CONTENTS Digital Principles & Logic Design
Section 6.5.1 - Designing with Programmable Array Logic
Let us consider that the following functions are to be realized using a PAL device.
F1 (A,B,C) = ( 1,2,4,5,7)
F2 (A,B,C) = ( 0,1,3,5,7)
Similar to designing with PLA, in the case of a PAL device some simplification must be carried out to reduce the total number of distinct product terms. Karnaugh maps for the above functions are drawn in Figures 6.24(a) and 6.24(b).
Figure 6.24(a) Map for function F1. - Figure 6.24(b) Map for function F2.
The Boolean expressions are
F1 (A,B,C) = AB' + AC + B'C + A'BC' and
F2 (A,B,C) = C + A'B'.
To use the PAL device as illustrated in Figure 6.23 for realization of the above expressions, it may be noted that a problem occurs that the specified PAL device has at the most three product terms associated with one OR gate, whereas one of the given functions F1 has four product terms. However, realization of the functions are achievable with the specified PAL device by the following method.
Let the above expressions be rewritten as
F1 (A,B,C) = F3 + B'C + A'BC'
F2 (A,B,C) = C + A'B'
where, F3 = AB' + AC.
Now there are three functions each of which contains no more than three product terms and these can be realizable by the specified PAL. The connection diagram of PAL is illustrated in Figure 6.25.
Figure 6.25
Here, one subfunction F3 has been generated with two product terms, and this sub-function is connected to one of the inputs to realize the final function F1. To realize F2, only two terms need to be generated. Since a three-input OR gate is used, the input must be kept at logic 0, so as not to affect the F2 output. This is achieved by keeping all the fuses intact to the AND gate that serves as the third input to the OR gate which is indicated by an '×' mark on the AND gate in Figure 6.24. With a variable and its complement as inputs an AND gate always produces logic 0.
It should be noted that the PAL device as demonstrated here is too small for the practical point of view. Similar to a PLA device, a practical PAL device contains at least ten inputs and about fifty product terms. This small and simple PAL device has been illustrated here only to show its general internal architecture and how the combinational circuits are realized. Simplification of Boolean functions should be carried out and special attention must be given while selecting the minimal terms as the number of OR gates is limited as well as limited product terms are connected to them.
With the fast advancement of technology, various types of programmable logic devices are being developed to meet the users desire. Programmable logic devices are also available with flip-flops. Some of the useful programmable devices are mentioned here.
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