From The Verilog Hardware Description Language, Fifth Edition
2.7 Finite State Machine and Datapath
We've used the language to specify combinational logic and finite state machines. Now we'll move up to specifying register transfer level systems. We'll use a method of specification known as finite state machine and datapath, or FSM-D. Our system will be made up of two parts: a datapath that can do computations and store results in registers, and a finite state machine that will control the datapath.
2.7.1 A Simple Computation
We begin with a simple computation and show how to specify the logic hardware using Verilog. The computation is shown below in a C-like syntax:
... for (x = 0, i = 0; i < = 10; i = i + 1) x = x + y; if (x < 0) y = 0; else x = 0; ...
The computation starts off by clearing x and i to 0. Then, while i is less than or equal to 10, x is assigned the sum of x and y, and i is incremented. When the loop is exited, if x is less than zero, y is assigned the value 0. Otherwise, x is assigned the value 0. Although simple, this example will...
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