BOOK_CONTENT
From High Performance Devices: Proceedings of the 2004 IEEE Lester Eastman Conference

STEVEN EUGENE TURNER and DAVID E. KOTECKI
Department of Electrical & Computer Engineering University of Maine, Orono, ME 04469-5708, USA

High-speed accumulators are frequently used as a benchmark of the high-speed performance and ability to yield large scale circuits in InP double hetereojunction bipolar (DHBT) processes. In previous work, we reported test results of an InP DHBT 4-bit accumulator with 624 transistors operating at 41 GHz clock frequency with a power consumption of 4.1W. In this work, we report on modifications that allow the circuit to operate at a lower supply voltage and a corresponding lower power consumption. Simulation results for this modification indicate that a 16% power reduction can be obtained, while maintaining a high-speed operating frequency of 40 GHz.

1. Introduction

High-speed accumulator circuits are a critical component of direct digital synthesizers (DDS), which are useful for generating frequency-agile waveforms with complex modulation. To allow direct generation of these waveforms at radio frequencies up to X-band, the accumulator circuit must operate at clock rates ?30 GHz. The accumulator must also have a wide bit width in order to provide adequate frequency resolution, thus requiring transistor counts approaching 5000 devices. The accumulator is a good benchmark of the ability to implement fast circuits with high integration levels in a given semiconductor process. For purposes of this research, we report accumulator benchmarks based on the InP DHBT process reported by Vitesse.1 These devices have f t and f max both over 300 GHz, and use a self-aligned,...

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