Trade-Offs in High-Speed Serial Link ICs

Overview

Serial IOs are widely used to expand the system bandwidth in communication systems. This paper provides an overview of serial IO design trade-offs with regard to power, cost, and performance. Circuit techniques are discussed to achieve low jitter and high bandwidth.

Keywords: SerDes, Serial IO, Clock Generation, Clock and Data Recovery (CDR), Highspeed Transceiver, Multi-phase, Jitter, Broadband.

1. Introduction

A wide range of applications nowadays use serial interfaces to achieve high-speed data transmission. Table 1 is a brief summary on some of the popular applications involving serial data communications, all of which feature an embedded clocking scheme, and differential signaling (electrical interface) to achieve high-speed transmission. In comparison with early parallel data bus technologies such as PCI, PCIX, or parallel ATA, a serial link is less susceptible to crosstalk, ground bounce, and clock skew because of the embedded clocking scheme and differential signaling, therefore can achieve much higher data rates over a considerably longer transmission distance. To this date, high-speed serial I/Os have emerged to become a part of routine design in CMOS ICs for high speed high bandwidth computing and communication systems such as computer chipsets and network processors.