From High-Speed Optical Transceivers: Integrated Circuits Designs And Optical Devices Techniques

Shenggao Li [1]
Intel Corporation
Fremont, CA 94538/USA
lisg@ieee.org

Overview

Serial IOs are widely used to expand the system bandwidth in communication systems. This paper provides an overview of serial IO design trade-offs with regard to power, cost, and performance. Circuit techniques are discussed to achieve low jitter and high bandwidth.

Keywords: SerDes, Serial IO, Clock Generation, Clock and Data Recovery (CDR), Highspeed Transceiver, Multi-phase, Jitter, Broadband.

[1]44235 Nobel Dr., Fremont, CA 94538

1. Introduction

A wide range of applications nowadays use serial interfaces to achieve high-speed data transmission. Table 1 is a brief summary on some of the popular applications involving serial data communications, all of which feature an embedded clocking scheme, and differential signaling (electrical interface) to achieve high-speed transmission. In comparison with early parallel data bus technologies such as PCI, PCIX, or parallel ATA, a serial link is less susceptible to crosstalk, ground bounce, and clock skew because of the embedded clocking scheme and differential signaling, therefore can achieve much higher data rates over a considerably longer transmission distance. To this date, high-speed serial I/Os have emerged to become a part of routine design in CMOS ICs for high speed high bandwidth computing and communication systems such as computer chipsets and network processors.

Table 1: Some representative high-speed serial interfaces

Standard

Data Rate (Gbps)

Description

SONET

9.95

Telecomm, OC192

OC192 over FEC

10.71

ITU G.709

10GE

10.31

802.3ae Ethernet, Datacomm for WAN/MAN

10GE over FEC

11.09

ITU G.709

10G Fiber channel

10.52

Storage area...


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Topics of Interest

CICERO S. VAUCHER Philips Research Labs, Prof. Holstlaan 4, 5656AA Eindhoven, Netherlands cicero.vaucher@philips.com JAN-PETER FRAMBACH Philips Semiconductors, Nijmegen, Netherlands...

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