6.1 Introduction

In previous chapters we have developed what we believe is a highly accurate delay model: the degradation delay model (DDM). We have also presented a new algorithm to handle the inertial effect in Sec. 3.4.2. To be able to exploit the model's benefits we need to include it in a logic-level simulation tool. Conventional logic-level simulators like the VHDL or Verilog standard simulators, are not suited to implement the DDM nor the new inertial effect handling algorithm. Regarding the DDM, extra information not present in conventional event-driven simulators is necessary to take account of the degradation effect. On the other hand, the new inertial effect algorithm is threshold-based instead of delay-based, as implemented in conventional approaches.

For these reasons, we have developed a new logic-level simulation tool which is able to implement the special characteristics of the DDM and the new inertial effect algorithm, besides the traditional techniques. This simulator is named HALOTIS, which stands for High Accuracy LOgic Timing Simulator. Among the main features of HALOTIS are its modularity and object-oriented design. These make it possible to implement a variety of delay models apart from the DDM, which is useful for making comparisons between them. Furthermore, it can be easily extended with new delay models. HALOTIS reads Verilog format for compatibility with existing commercial tools, but the parser side is also modular and can be extended to support other formats. Although HALOTIS is still in active development, it...