Passive Equalization of Test Fixtures for High-Speed Digital Measurements with Automated Test Equipment

Automated test equipment (ATE) is used extensively in production test and device characterization of integrated circuits (ICs). With future devices forecasted to contain hundreds of I/O cells operating at speeds from 5Gb/s to 10Gb/s, the challenge to test those devices with an ATE system is becoming more complex. The speed bottleneck is moving from the pin electronics of the ATE to the test fixture connecting the ATE to the device under test (DUT). The layout of the test interface will require thinner and longer signal traces which will have an unacceptable loss for the required data rates. This challenge will require the use of compensation techniques to address the increased loss of the signal traces. This article presents one strategy to address this challenge by integrating passive equalization in the test-fixture signal trace. Current state-of-the-art integrated circuits (ICs) that are in volume production already contain tens of I/O cells running at speeds between 5Gb/s and 10Gb/s [1]. With the increased availability and quality of these high-speed I/O cells in standard CMOS processes, this trend will continue with near-future devices containing hundreds of these I/O cells. Device pin counts will then be above one thousand, when taking into account all the pins (high-speed, power, low-speed, etc...).