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Thermal Measurement and Modeling Of Multi-Die Packages
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Thermal Measurement and Modeling Of Multi-Die Packages
 
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Thermal Measurement and Modeling Of Multi-Die Packages
From Flomerics Inc.
 

 
Thermal measurement and modeling of multi-die packages with vertical (stacked) and lateral arrangement became a hot topic recently in different fields like RAM chip packaging or LEDs and LED assemblies. In our present study we present results for a more complex structure: an opto-coupler device with 4 chips in a combined lateral and vertical arrangement. The paper gives an overview of measurement and modeling techniques and results for stacked and MCM structures. It describes actual measurement results along with our structure function based methodology which helps validating the detailed model of the package being studied. Also, we show how one can derive junction-to-pin thermal resistances with a technique using structure functions. Thermal measurement and modeling of multi-die packages became a hot topic in recent years. A detailed, comprehensive overview has been given recently [1] where different measurement and modeling techniques have been referred to. Nowadays, besides IR techniques (e.g. [2]) the mainstream characterization technique seems to be the JEDEC JESD51-1 based electrical test method [3], yielding either thermal resistance values only (static characterization – see e.g. [4], [5]) or providing the dynamic description of the packaged multi-die system by means of thermal impedances in various forms (full set of real heating or cooling curves, complex loci – see e.g. [6] or structure functions as presented in [7]).

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Thermal Measurement and Modeling Of Multi-Die Packages (.pdf) - Test and Measurement
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