Appendix 3A: Single-Ended Explanation of Offset Currents

Appendix 3A: Single-Ended Explanation of Offset Currents

The single-ended interconnection that is shown in Figure 3A.1 provides a graphically simpler explanation of the offset current effects in a PLL. In a locked condition, the charge on the feedback capacitor remains constant, and this provides a constant tune voltage to the VCO. Consequently, zero current should flow through the feedback capacitor. A bias current from the operational amplifier draws charge away from the feedback capacitor and produces an error. The loop cancels this error by producing a wider pulse out of the phase detector, which generates a current that counteracts the bias current from the operational amplifier. This counteracting current maintains the loop in the locked condition.

Figure 3A.1: Schematic of offset currents in a single-ended loop filter

Consequently, using operational amplifiers with higher-bias currents causes the loop to produce a wider pulse width out of the phase detector to maintain lock. This larger pulse width produces higher reference sidebands because the energy in the first harmonic of a pulse increases with wider pulse widths, as shown in a Fourier series of a pulse. Adding an additional current source as shown in

Figure 3A.1 is one way to cancel the bias current from the operational amplifier and reduce the pulse width out of the phase detector. The differential interconnection requires significantly less bias current. Consequently, the differential interconnection, as indicated in the text, is the preferred method.