The PIC16C5X/XX microcontrollers from Microchip Technology Inc., provide significant execution speed and code-compaction improvement over any other 8-bit microcontroller in its price range. The superior performance of the PIC16C5X/XX microcontrollers can be attributed primarily to its RISC architecture. The PIC16C5X/XX devices employ a Harvard architecture (i.e., has separate program mem-ory space and data memory space [8-bit wide data]). It also uses a two stage pipelining instruction fetch and execution. All instructions are executed in a single cycle (200 ns @ 20 MHz clock) except for program branches which take two cycles, and there are only 33 instructions to remember. Separation of program and data space allows the instruction word to be optimized to any size (12-bit wide for PIC16C5X devices and 14-bit wide for PIC16CXX devices).This makes it possible, for example, to load an 8-bit immediate value in one cycle. First, because there is no conflict between instruction fetch and data fetch (as opposed to von Neumann architecture) and secondly because the instruction word is wide enough to hold the 8-bit data. In the following sections we will compare the PIC16C5X/XX devices @ 20 MHz with: ? SGS-Thomson ST62 @ 8 MHz ? Motorola MC68HC05 @ 4.2 MHz ? Intel 8051 @ 20 MHz ? Zilog Z86CXX @ 12 MHz ? National COP800 @ 20 MHz Several coding examples will be considered. While the comparisons are not entirely scientific, they will demonstrate to the reader the relative superior performance of the PIC16C5X/XX devices. The examples chosen are used frequently in microcontroller applications.