Bridging the PCI Express Interconnect Divide

While the transition from PCI and PCI-X to PCI Express® took some time, few that will argue that PCI Express is now the ubiquitous interconnect available on the latest chipsets and processors. Initial processor offerings provided both PCI Express and PCI/X (i.e. PCI or PCI-X), but PCI/X is quickly disappearing from the processor landscape due to the inherent cost in terms of pin count. However, while processors may have made the transition to PCI Express, the same doesn't apply for many peripherals. This is especially true for legacy I/O peripherals as well as the numerous ASICs and FPGAs that were designed around the PCI and PCI-X standards. From a block diagram perspective, solving this new interconnect mismatch between PCI Express-based processors and legacy peripherals is straightforward. Simply use a block entitled "PCI Express to PCI Bridge" and the job is done. But putting a bridge in a block diagram is much different than solving the interconnect challenge in a way that doesn't compromise the resultant system in terms of power, performance, cost and reliability.