From Silicon Labs
FPGA-based systems have become common and are appropriate for many applications. However, by their nature, FPGAs are power-hungry devices with complex power delivery requirements and multiple voltage rails.
When FPGA power consumption increases, performance requirements on sensitive analog and mixed-signal subsystems also increase, particularly on clocking subsystems that provide low jitter timing references for the FPGA and other board-level components.
This white paper describes how to use clock sources with integrated power supply noise rejection, designers can simplify power supply design and mitigate these design challenges.
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