Optical Network Analysis and Emulation

Featured Product from GL Communications, Inc.

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GL's LightSpeed1000™ hardware platform (PCIe Card) is capable of OC-3/12 and STM-1/4 wire-speed processing on quad optical ports for functions such as wire-speed recording and wire-speed playback of Unchannelized and Channelized ATM, PoS, and RAW Traffic.

Two ports out of the 4 ports are meant for SONET/SDH unchannelized and unframed data. The remaining two ports are meant for SONET/SDH channelized data of carrying many independent unframed/framed T1, E1, T3, and E3 streams.

The LightSpeed1000™ comes with software for overall monitoring, BERT, emulation, and protocol analysis with a price tag that compares very favorably with similar test instruments at three times the price.

Main Features

  • Wirespeed processing of ATM, PoS or RAW data for Tx and Rx for both ports (PCIe card only).
  • Software selectable OC-3 / OC-12, or STM-1 / STM-4 for Unchannelized ATM, PoS or Transparent Traffic, and Channelized T1, E1, T3, E3 traffic.
  • Ability to capture/playback to/from disk at full rate in both directions for all ports.  Simultaneous synchronous capture is possible on all optical ports. The captured files can be played back to reproduce the traffic.
  • Comprehensive transmit/receive testing capabilities; transmitting and verifying data with incrementing sequence numbers with each packet/cell
  • Protocol Analyzer for unchannelized ATM (AAL2, AAL5), UMTS, and PPP (IP and higher layer protocols) stream, and channelized protocols such as ISDN, SS7, CAS, and more.
  • Easy to use and flexible Bit Error Rate Test application for ATM, PoS, and RAW
  • Complex and flexible hardware based filtering options: sixteen 128 bit independently filters with bit masks, for both ports with AND/OR include/exclude conditions
  • Hardware based precise time stamping of cells / packets with 10 nsec resolution, 1 ppm accuracy
  • Single mode or multi-mode fiber SFP support
  • High performance x4 PCIe interface with optimized DMA to transmit and receive packets to/from PC memory
  • Add latency to ATM or PoS traffic (adjustable from 1 – 500 ms).
  • Flexible DMA circular buffer architecture to read and write cells and packets at wire-speed
  • Multiple cards per system for super high capacity monitoring and test system.
  • API Toolkit to develop user specific applications
  • Optional onboard memory (DDR2) – up to 2 GB
  • Hardware independent of higher level protocols for easy adaptation of future protocols
  • Field upgradable firmware
  • Supports Windows® and Linux operating systems

 

Specifications:

Interfaces:

  • High Performance x4 PCIe Compliance with optimized DMA to perform Rx and Tx packets to/from PC memory.
  • 4 Optical Ports
  • 2 Unchannelized Ports (STM1/OC3 and STM4/OC12)
  • 2 Channelized Ports (STM1/OC3)

Alarm LEDs:

  • LOS – LOS (Loss of Signal) is a physical layer error, which indicates loss in optical signal.
  • LOF - LOF (Loss of Frames) becomes active when receiving interface detects errors in the framing pattern for three milliseconds. This will be indicated using the frame alignment bytes A1 and A2. LOF is cleared when two consecutive valid A1/A2 framing patterns are received.
  • User – A user-defined LED can be configured by the user as per the requirements.

Bus Interface:

  • PCIe Specification 1.2 Compliant

Traffic

  • Structured (T1, E1. DS0)
  • Unstructured (OC3/STM1, OC12/STM4)
  • Transparent Generic Framing Procedure (GFP) (Raw)
  • Hardware Filters to filter out and allow only traffic of interest

Regulatory and Compliance

  • Telecom (OC3): Telcordia GR-253 (SONET)
  • ITU-T G.707 (SDH), G.783 (03/06)

Channelized Protocols (Structured)

  • High-Level Data Link Control (HDLC)
  • Point-to-Point Protocol (PPP), RFC 1662
  • Multilink PPP (MLPPP), RFC 1990
  • Frame Relay, RFC 1490
  • Multilink support over Frame Relay (FRF.12) and MLPPP
  • ATM IMA
  • GSM, TRAU, GPRS, UMTS over ATM
  • SS7, ISDN, CAS, SS1, SSM
  • V5.x, DCME, FDL (T1 Interface only)

Channelized File based High Throughput HDLC Record/Playback (HdlcHpio)

Channelized Multi-Channel HDLC Emulation and Analysis (HDLCTerr)