CES for Expedition PCB Training

Service Detail from Mentor, a Siemens Business


In this course, Mentor PCB design experts will teach you to use CES as a constraint system in the DxDesigner-to-Expedition PCB flow, giving you the detailed knowledge you need to define design constraints.

You will learn to quickly document your design constraints in a spreadsheet paradigm with formulas, references, hierarchy and reuse. Hands-on lab exercises will reinforce lecture topics and facilitate efficient constraint definition for complete design, e.g., complex buses, Gigabit channels, DDR, etc.

What you'll learn

Lecture/demonstration discussions will be followed by hands-on lab experiences to reinforce knowledge gained from the lecture material. This course steps you through the following lectures and exercises:

CES overview

  • Using the CES graphical user interface and customizing it
  • Define, navigate and manipulate constraints hierarchies in CES

Mechanical constraints

  • Partition design data using net classes, constraint classes and schemes
  • Set up mechanical constraints such as trace widths, via assignments, and clearances

High-speed constraints

  • Assign physical high-speed constraints such as minimum/maximum/matched delays, delay formulas, custom or complex topologies, differential pairs and parallelism rules to nets/net groups
  • Autoroute constrained nets and evaluate routing results

Design validation and constraint reuse

  • Validate the layout against constraints directly within the editor
  • Employ constraint templates to reuse already-defined constraints in other designs