Red Pitaya in synchrotrone SOLEIL
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Recently there has been an article published in Nature Physics which describes the use of Red Pitaya in a project of relativistic electron bunches in synchrotron light sources. This project was done at French national synchrotron radiation facility SOLEIL. We are proud to say that Red Pitaya was not not just a part of the experiment but the FPGA was the main component of the control.
Relativistic electron bunches used in synchrotron light sources are complex media, in which patterns might form spontaneously. There have been a lot of studies conducted over the past decades because of very practical reasons. The patterns appear cpontaneously during an instability and this increases the terahertz radiation power by factor 10,000 or more. The irregularity of the patterns prevented applications of this powerful source. In this study it has been shown how principles from chaos control theory allow us to generate regular spation-temporal patterns, stabilizing the emitted terahertz power. Regular unstable solutions are expected to coexist with the undesired irregular solutions, and may thus be controllable using feed-back control. We demonstrate the stabilization of such regular solutions in the Synchrotron SOLEIL storage ring. Operation of these controlled unstable solutions enables new designs of high-charge and stable synchrotron radiation sources.
The terahertz signal is monitored by an InSb hot-electron bolometer (Infrared Laboratories), with a 1 μs response time and a.c. output coupling. The bolometer detects the terahertz coherent synchrotron radiation emitted at the AILES beamline of synchrotron SOLEIL. The bolometer signal is then digitized and processed using a low-cost FPGA board (Red Pitaya STEMlab 125-14 board, based on the Xilinx Zynq 7010 SOC-FPGA). The digitization is performed by one of the two analog-to-digital converters of the FPGA board at 125 MS s−1, with a 50 MHz bandwidth. The acquired signal is first digitally low-pass-filtered using a first-order filter (with a cutoff frequency fc = 3 kHz), and resampled at 1 MS s−1. The FPGA uses this filtered signal X(t) to compute the feedback signal ΔV = G[X(t) − X(t − τ)]. This digital signal is then converted to an analog signal, using one of the two digital-to-analog converters of the FPGA board. In addition, the bolometer and control signals are also monitored using a 1 GHz oscilloscope (Lecroy WR104MXI). The bolometer, oscilloscope and FPGA (and its control computer) are placed in the AILES beamline area, and the analog control signal provided by the FPGA is transported to the low-level RF (LLRF) system of SOLEIL located a few tens of metres from the FPGA, using a coaxial cable. This signal is used to modulate the amplitude of one of the RF accelerating cavities.