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ADF4368 Frac-N Wideband Synthesizer:Analog Devices

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The ADF4368 is a high performance, ultra-low jitter, integer-N and fractional-N phase-locked loop (PLL) with integrated VCO ideally suited for frequency conversion applications. 

The high performance PLL has a figure of merit of −239 dBc/Hz, very low 1/f noise of normalized −287 dBc/Hz and high PFD frequency that can achieve ultra-low in-band noise and integrated jitter. The ADF4368 can generate any frequency from 800 MHz to 12.8 GHz without an internal doubler, which eliminates the need for sub-harmonic filters. The Σ-Δ modulator includes a 25-bit fixed modulus that allows hertz frequency resolution and an additional 17-bit variable modulus, which allows even finer resolution and flexibility for frequency planning. The 9 dBm output power at 12.8 GHz in single-ended configuration with 16 step power adjust feature makes it very useful for any application.

The simplicity of the ADF4368 eases development time with a simplified serial-peripheral interface (SPI) register map, external SYNC input, and repeatable multichip phase alignment both in integer mode and fractional mode.

 

FEATURES
- Output frequency range: 800 MHz to 12.8 GHz
- Jitter < 30 fsRMS fOUT = 9.001 GHz, fREF = fPFD = 250 MHz, fractional mode
- Wideband phase noise floor: −160 dBc/Hz at 12.8 GHz
- PLL specifications:
     - Normalized in-band phase noise floor
          - −239 dBc/Hz: integer, −237 dBc/Hz: fractional mode
     - Normalized 1/f phase noise floor
          - −287 dBc/Hz: normalized to 1 Hz
          - −147 dBc/Hz: normalized to 1 GHz at 10 kHz
- 625 MHz phase detector frequency integer mode
- 250 MHz phase detector frequency fractional mode
- 25-bit fixed, 49-bit combined fractional modulus
- 4 GHz reference input frequency
- Typical −95 dBc PFD spurs 

APPLICATIONS
- Wireless infrastructure
- Test and measurement
- Aerospace and defense