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On-Demand Webinar:

Upgrade to a Custom ASIC

The custom ASIC process has become a much less costly and risky proposition over the last two decades with easy-access and cost-effective tools, services and IP. Join this webinar to learn how to affordably and reliably bring a custom ASIC to market, and start reaping the power, performance, and cost benefits.

Originally presented: March 13, 2019
Duration: 1 hour
Presented by:


Developing a custom ASIC offers many compelling advantages. For some it is adding intelligence to make a device more compelling; for others, it's integrating a CPU and discretes onto a chip to reduce bill-of-material cost and footprint, improve performance, or protect IP.

This webinar will focus on the practical considerations of getting a custom ASIC built, particularly for low to medium volume products. Attendees will benefit from the knowledge and experience of speakers from Arm, imec.IC-link and Mentor Graphics.

Arm, imec.IC-link and Mentor are world leaders in the ASIC ecosystem and have joined forces to help designers, engineering directors/managers, and product managers understand the latest options to deliver a product based on a custom ASIC.

Key Takeaways

  • Learn about process nodes and their typical costs
  • Understand the differences between multi-project wafers (MPW), multi-layer masks (MLM) or full masks
  • Discover the benefits of complete ASIC supply chain management


Chun Chi Lin, Sales Development Manager, imec

Chun Chi Lin is a sales development manager of imec.IC-link. In this role, he is responsible for developing solutions-oriented for customers' ASIC projects.

During his 18-year career in the semiconductor industry, Chun Chi has been prospecting with customers to break down old boundaries and achieve best silicon solutions in IoT/industrial/automotive applications.

Chun Chi earned his master degree in electronics and electrical engineering from Central University in Taiwan, and MBA degree from Glasgow University in the U.K.

Jeff Miller, Lead Strategist and Product Manager, Mentor, a Siemens Business

Jeff Miller is a lead strategist and manages Tanner's analog and mixed signal product lines at Mentor, a Siemens Business. Jeff started as an engineer at Tanner Research in 2002 and became product manager of Tanner EDA in 2007. Prior to joining Tanner EDA, Jeff worked as a design engineer on analog, digital, and mixed signal chip development projects for the defense, medical and commercial markets. Jeff holds a bachelors in engineering from Harvey Mudd College.

Richard York, Senior Director, Design House Enablement, Arm

Richard York is the senior director of design house enablement at Arm, responsible for supporting and developing the relationships with design service companies worldwide. Richard helps ensure that the ASIC design services community addresses the rapidly growing custom system-on-chip (SoC) design market with Arm technology, so that many more manufacturers and systems companies can take advantage of the benefits of custom SoCs.

Richard joined Arm in 1994 and was closely involved in the design of early Arm processors before moving into marketing in 2000. Richard has previously managed the Cortex-M and Cortex-R processor families and more recently drove Arm's segment marketing in automotive and embedded.