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Upcoming Webinar:

DDR Memory Systems: Design Verification and Debugging

Register to get best practices of DDR memory system design verification and debugging using an oscilloscope.



Date: November 6, 2020
Time: 10 AM EST (7 AM PST / 4:00 PM CET)
Duration: 1 hour
Presented by:

Overview

This webinar discusses best practices of performing DDR memory system design verification and debugging with an oscilloscope.

Design and verification engineers will learn the importance of ensuring a stable operation and of reducing the risk of failure after any change over the product's lifetime. Both require a solid characterization of the memory interface.

We will be discussing test and tool requirements such as bandwidth, trigger and probing, which help with identifying jitter, timing and noise issues. With the help of the R&S®RTP high-performance oscilloscope, we will showcase practical measurement examples.

Key Takeaways

  • Learn the importance of ensuring a stable operation
  • Reduce the risk of failure after any change over the product´s lifetime
  • Discover test and tool requirements and insides about Rohde & Schwarz oscilloscopes

Speakers

Hermann Ruckerbauer, CEO, EyeKnowHow

Hermann Ruckerbauer, Owner of EKH - EyeKnowHow, has over 20 years of experience in high-speed measurement and simulation, especially on DRAM-related interfaces. EyeKnowHow helps the industry by offering consulting, simulation, measurements and training for all kind of high-speed serial interfaces. After receiving his bachelor's degree in microsystems technology from the Regensburg University of Applied Sciences, he was doing design analysis and application testing for several memory generations at Siemens/Infineon.

His latest activity, before founding his own company, was the definition of the DDR4 signaling standard within JEDEC for Qimonda. With the background of DRAM internal functionally, system application requirements and high-speed signaling, he is supporting any kind of high-speed interface implementations (e.g. for 10 Gigabit Ethernet, PCIe, SATA, USB and others) with a focus on memory standards. He holds many patents and was awarded by Infineon in 2005 in the category "Outstanding Single Patent" for the patent on the "Temperature-dependent self refresh" in DDR memory devices.

Johannes Ganzert, Application Engineer Oscilloscopes, Rohde & Schwarz

Johannes Ganzert is a senior applications engineer for oscilloscopes at Rohde & Schwarz in Munich, Germany. After graduation at the Technical University of Munich, he joined Rohde & Schwarz as a development engineer for digital hardware and software. Over time, Johannes Ganzert collected a vast experience in RF and digital applications, particularly high-speed digital design and serial buses. He is an active participant in several standardization consortia like OPEN Alliance and USB-IF.