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On-Demand Webinar:

Partitioning Designs into Multiple FPGAs with Veloce proFPGA Prototyping Solution

In this webinar, we will discuss the use of prototyping software, VeloceOS for Prototyping (VPS), to compile, partition and route your design, regardless of size, into FPGA prototypes with excellent performance quickly, efficiently, and automatically.

Originally presented: September 26, 2023
Duration: 1 hour
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Whenever a chip, subsystem or block is larger than the capacity of a single FPGA, which today is 30-40 Mgates, that functionality must be partitioned and mapped into multiple FPGAs. In nearly all cases, the signals interconnecting the functionality between the FPGAs will need to be multiplexed as the number of those signals exceeds the physical connectivity available between any 2 FPGAs. If partitioning, routing and multiplexing signal connectivity were performed manually, it would require a significant effort – man-weeks – to achieve optimal utilization of the FPGA resources and the multi-megahertz performance expected of an FPGA prototype. As prototyping begins before the design is complete, this effort will be invested every time a new drop of the design is ready. Man-weeks turn into man-months and into man-years. Schedules slip as validation and software development lag the ability to generate updated prototypes of the chip functionality. Corners are cut in optimizing the performance of the prototype to keep up with the demand for the latest version of the design code further compromising schedule or quality constraints.

Key Takeaways

  • Establish an efficient approach to partitioning, routing, and multiplexing signal connectivity
  • Discover how to limit schedule slips when generating prototype updates of the chip functionality
  • Learn how to achieve optimal utilization of the FPGA resources and the multi-megahertz performance expected of an FPGA prototype


Stephen Bailey, Director of Product Management, Siemens EDA

In a career spanning three decades, Bailey created HDL simulators in R&D, assisted customers in deploying and using verification solutions as an applications engineer and consultant, chaired IEEE and Accellera industry standards committees on VHDL and UPF, and managed product strategy and marketing for several functional verification solutions. Prior to his EDA career and after earning his BS and MS in computer science, he developed real-time software tooling for the mil-aero industry. Bailey has authored numerous papers over his career and served as technical program and conference chair for industry conferences.